SLVSCL3E June   2014  – May 2019 TPS65283 , TPS65283-1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Schematic
    1.     Efficiency, Vin = 12 V, PSM
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Switch Detailed Description
        1. 9.3.1.1 Overcurrent Condition
        2. 9.3.1.2 Reverse Current and Voltage Protection
        3. 9.3.1.3 nFAULT Response
        4. 9.3.1.4 UVLO
        5. 9.3.1.5 Enable and Output Discharge
        6. 9.3.1.6 Power Switch Input and Output Capacitance
        7. 9.3.1.7 Programming the Current-Limit Threshold
      2. 9.3.2 Buck DC-DC Converter Detailed Description
        1. 9.3.2.1  Output Voltage
        2. 9.3.2.2  Adjustable Switching Frequency
        3. 9.3.2.3  Synchronization
        4. 9.3.2.4  Error Amplifier
        5. 9.3.2.5  Slope Compensation
        6. 9.3.2.6  Enable and Adjusting UVLO
        7. 9.3.2.7  Internal V7V Regulator
        8. 9.3.2.8  Short Circuit Protection
          1. 9.3.2.8.1 High-Side MOSFET Overcurrent Protection
          2. 9.3.2.8.2 Low-Side MOSFET Overcurrent Protection
        9. 9.3.2.9  Bootstrap Voltage (BST) and Low Dropout Operation
        10. 9.3.2.10 Output Overvoltage Protection (OVP)
        11. 9.3.2.11 Power Good
        12. 9.3.2.12 Power-Up Sequencing
        13. 9.3.2.13 Thermal Performance
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation With VIN < 4.5 V (Minimum VIN)
      2. 9.4.2 Operation With EN Control
      3. 9.4.3 Operation at Light Loads
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Voltage Setting
        2. 10.2.2.2 Bootstrap Capacitor Selection
        3. 10.2.2.3 Inductor Selection
        4. 10.2.2.4 Output Capacitor Selection
        5. 10.2.2.5 Input Capacitor Selection
        6. 10.2.2.6 Minimum Output Voltage
        7. 10.2.2.7 Compensation Component Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Layout Recommendation
      2. 12.1.2 Power Dissipation and Junction Temperature
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.3 Operation at Light Loads

The devices are designed to operate in high-efficiency PSM under light load conditions. Pulse skipping is initiated when the switch current falls to 0 A. During pulse skipping, the low-side FET is turned off when the switch current falls to 0 A. The switching node (LX) waveform takes on the characteristics of DCM operation and the apparent switching frequency decreases.