SLVSCL3E June   2014  – May 2019 TPS65283 , TPS65283-1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Schematic
    1.     Efficiency, Vin = 12 V, PSM
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Switch Detailed Description
        1. 9.3.1.1 Overcurrent Condition
        2. 9.3.1.2 Reverse Current and Voltage Protection
        3. 9.3.1.3 nFAULT Response
        4. 9.3.1.4 UVLO
        5. 9.3.1.5 Enable and Output Discharge
        6. 9.3.1.6 Power Switch Input and Output Capacitance
        7. 9.3.1.7 Programming the Current-Limit Threshold
      2. 9.3.2 Buck DC-DC Converter Detailed Description
        1. 9.3.2.1  Output Voltage
        2. 9.3.2.2  Adjustable Switching Frequency
        3. 9.3.2.3  Synchronization
        4. 9.3.2.4  Error Amplifier
        5. 9.3.2.5  Slope Compensation
        6. 9.3.2.6  Enable and Adjusting UVLO
        7. 9.3.2.7  Internal V7V Regulator
        8. 9.3.2.8  Short Circuit Protection
          1. 9.3.2.8.1 High-Side MOSFET Overcurrent Protection
          2. 9.3.2.8.2 Low-Side MOSFET Overcurrent Protection
        9. 9.3.2.9  Bootstrap Voltage (BST) and Low Dropout Operation
        10. 9.3.2.10 Output Overvoltage Protection (OVP)
        11. 9.3.2.11 Power Good
        12. 9.3.2.12 Power-Up Sequencing
        13. 9.3.2.13 Thermal Performance
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation With VIN < 4.5 V (Minimum VIN)
      2. 9.4.2 Operation With EN Control
      3. 9.4.3 Operation at Light Loads
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Voltage Setting
        2. 10.2.2.2 Bootstrap Capacitor Selection
        3. 10.2.2.3 Inductor Selection
        4. 10.2.2.4 Output Capacitor Selection
        5. 10.2.2.5 Input Capacitor Selection
        6. 10.2.2.6 Minimum Output Voltage
        7. 10.2.2.7 Compensation Component Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Layout Recommendation
      2. 12.1.2 Power Dissipation and Junction Temperature
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

24 Leads
Plastic VQFN (RGE)
(Top View)
TPS65283 TPS65283-1 po_SLVSCL3.gif
(There is no electric signal down boned to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.)

Pin Functions

PIN DESCRIPTION
NAME NO.
PGOOD2 1 Power good indicator pin. Asserts low if the output voltage of buck2 is out of range due to thermal shutdown, dropout, over-voltage, EN, shutdown, or during slow start.
EN1 2 Enable pin for buck 1. A high signal on this pin enables buck1. For a delayed start-up, add a small ceramic capacitor from this pin to ground.
EN2 3 Enable pin for buck 2. A high signal on this pin enables buck2. For a delayed start-up, add a small ceramic capacitor from this pin to ground.
ROSC/SYNC 4 Automatically select clock frequency program mode and clock synchronization mode. Program the switching frequency of the device from 200 kHz to 2 MHz with an external resistor connecting to the pin. In clock synchronization mode, the device automatically synchronizes to an external clock applied to the pin.
SW_EN 5 Enable power switch. Float to enable.
nFAULT 6 Active low open-drain output. Asserted during overcurrent or reverse-voltage condition of power switch.
SW_OUT 7 Power switch output
SW_IN 8 Power switch input
VIN2 9 Input power supply for buck2. Connect this pin as close as possible to the (+) terminal of input ceramic capacitor (10 µF suggested).
PGND2 10 Power ground connection. Connect this pin as close as possible to the (–) terminal of input capacitor of buck2.
LX2 11 Switching node connection to the inductor and bootstrap capacitor for buck2 converter. This pin voltage swings from a diode voltage below the ground up to input voltage of buck2.
BST2 12 Bootstrapped supply to the high-side floating gate driver in buck converter. Connect a capacitor (47 nF recommended) from this pin to LX2.
COMP2 13 Error amplifier output and loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the control loop of buck2 with peak current PWM mode.
FB2 14 Feedback sensing pin for buck2 output voltage. Connect this pin to the resistor divider of buck2 output. The feedback reference voltage is 0.6 V ±1%.
RSET 15 Power switch current limit control pin. An external resistor used to set current limit threshold of power switch. Recommended 9.1 kΩ ≤ RSET ≤ 80.6 kΩ.
AGND 16 Analog ground common to buck controller and power switch controller. AGND must be routed separately from high current power grounds to the (–) terminal of bypass capacitor of internal V7V LDO output.
FB1 17 Feedback sensing pin for buck1 output voltage. Connect this pin to the resistor divider of buck1 output. The feedback reference voltage is 0.6 V ±1%.
COMP1 18 Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the control loop of buck1 converter with peak current PWM mode.
BST1 19 Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (recommend 47 nF) from this pin to LX1.
LX1 20 Switching node connection to the inductor and bootstrap capacitor for buck1. This pin voltage swings from a diode voltage below the ground up to input voltage of buck1.
PGND1 21 Power ground connection. Connect this pin as close as possible to the (–) terminal of input capacitor of buck1.
VIN1 22 Input power supply for buck1 and internal analog bias circuitries. Connect this pin as close as possible to the (+) terminal of an input ceramic capacitor (10 µF suggested).
V7V 23 Internal linear regulator (LDO) output with input from VIN1. The internal driver and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. The output voltage level of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In PCB design, the power ground and analog ground should have one-point common connection at the (–) terminal of V7V bypass capacitor.
PGOOD1 24 Power good indicator pin. Asserts low if the output voltage of buck1 is out of range due to thermal shutdown, dropout, over-voltage, EN shutdown or during slow start.
PowerPAD™ — Exposed pad beneath the IC. Connect to the power ground. Always solder power pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. There is no electric signal down bonded to paddle inside the IC package.