Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 3-inch, four-layer PCB with 2-oz. copper used as example.
Place the decoupling capacitors right across PVIN, PVIN_VPP, and VLDOIN as close as possible.
Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to minimize EMI, and should be a width plane to carry big current, enough vias should be added to the PGND connection of output capacitor and also as close to the output pin as possible. Reserve some space between VDDQ choke and VPP choke, just minimize radiation crosstalk.
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace is recommended to reduce line parasitic inductance.
VPPSNS/VDDQSNS/VTTSNS could be 10 mil and must be routed away from the switching node, BST node or other high efficiency signal.
PVIN and PVIN_VPP trace must be wide to reduce the trace impedance and provide enough current capability.
Output capacitors for VTT and VTTREF should be put as close as output pin.