SLVSC10C October   2013  – April 2016 TPS65301-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 5-V Linear Regulator (5 VO)
      2. 6.6.2 3.3-V Linear Regulator Controller (3.3 VO)
      3. 6.6.3 1.2-V Linear Regulator Controller (1.2 VO)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Converter
        1. 7.3.1.1  PWM Operation
        2. 7.3.1.2  Voltage-Mode Control Loop
        3. 7.3.1.3  Output Voltage 5.45 V (VREG)
        4. 7.3.1.4  Switching Frequency (RT/CLK)
        5. 7.3.1.5  Boost Capacitor (BOOT)
        6. 7.3.1.6  Soft Start (SS)
        7. 7.3.1.7  Power-On Delay (DELAY)
        8. 7.3.1.8  Reset (nRST)
        9. 7.3.1.9  Thermal Shutdown
        10. 7.3.1.10 Reset Function
      2. 7.3.2 Linear Regulators
        1. 7.3.2.1 Fixed Linear Regulator Output (5 V)
        2. 7.3.2.2 Fixed Linear Regulator Controller (3.3 V)
        3. 7.3.2.3 Fixed Linear Regulator Controller (1.2 V)
        4. 7.3.2.4 Protected Sensor Supply Output (5VS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operational Mode
      2. 7.4.2 Buck Converter Modes of Operation
        1. 7.4.2.1 Modes of Operation
          1. 7.4.2.1.1 Continuous-Conduction Mode (CCM)
          2. 7.4.2.1.2 Discontinuous Mode (DCM)
        2. 7.4.2.2 Tracking Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Duty Cycle
        2. 8.2.2.2 Output Inductor Selection (L)
        3. 8.2.2.3 Output Capacitor Selection (CO)
        4. 8.2.2.4 External Schottky Diode (D) Power Dissipation
        5. 8.2.2.5 Input Capacitor (CI)
        6. 8.2.2.6 Loop Compensation
          1. 8.2.2.6.1 Loop-Control Frequency Compensation
            1. 8.2.2.6.1.1 Type III Compensation
            2. 8.2.2.6.1.2 PWM Modulator Gain K
            3. 8.2.2.6.1.3 Resistor Values
            4. 8.2.2.6.1.4 Gain of Amplifier
            5. 8.2.2.6.1.5 Poles and Zero Frequencies
        7. 8.2.2.7 Power Dissipation
          1. 8.2.2.7.1 Switch-Mode Power-Supply Losses
          2. 8.2.2.7.2 Linear Regulator (5V) and Sensor Supply (5VS)
          3. 8.2.2.7.3 Total Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Inductor (L)
      2. 10.1.2 Input Filter Capacitors (CI)
      3. 10.1.3 Feedback
      4. 10.1.4 Traces and Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resource
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The following guidelines are recommended for PCB layout of the TPS65301-Q1 device.

10.1.1 Inductor (L)

Use a low-EMI inductor with a ferrite-type shielded core. Other types of inductors may be used; however, they must have low-EMI characteristics and be located away from the low-power traces and components in the circuit.

10.1.2 Input Filter Capacitors (CI)

Input ceramic filter capacitors should be located in close proximity to the VIN pin. Surface-mount capacitors are recommended to minimize lead length and reduce noise coupling.

10.1.3 Feedback

Route the feedback trace such that there is minimum interaction with any noise sources associated with the switching components. Recommended practice is to ensure placing the inductor away from the feedback trace to prevent a source of EMI noise.

10.1.4 Traces and Ground Plane

All power (high-current) traces should be thick and as short as possible. The inductor and output capacitors should be as close to each other as possible. This reduces EMI radiated by the power traces due to high switching currents.

In a two-sided PCB it is recommended to have ground planes on both sides of the PCB to help reduce noise and ground-loop errors. The ground connection for the input and output capacitors and IC ground should be connected to this ground plane.

In a multi-layer PCB, the ground plane is used to separate the power plane (where high switching currents and components are placed) from the signal plane (where the feedback trace and components are) for improved performance.

Also arrange the components such that the switching-current loops curl in the same direction. Place the high-current components such that during conduction the current path is in the same direction. This prevents magnetic field reversal caused by the traces between the two half-cycles, helping to reduce radiated EMI.

10.2 Layout Example

TPS65301-Q1 PCB-layout_SLVSC10.gif Figure 22. PCB Layout