SLDS222C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Functional Block Diagram
  6. 5 Revision History
  7. 6 Description (continued)
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State

The system MCU can activate the ABIST when the device is in the DIAGNOSTIC, ACTIVE, or SAFE state through the ABIST_GROUPx_START control bits in the SAFETY_ABIST_CTRL register when the ABIST_SCHED_EN configuration bit in the SAFETY_CFG2 register is not set.

In SAFE and DIAGNOSTIC states, ABIST runs immediately after setting ABIST_GROUPx_START bit in SAFETY_ABIST_CTRL register. In ACTIVE state, if ABIST_SCHED_EN ="0", ABIST runs only once after the ABIST_SCHED_DLY has expired. In ACTIVE state, if ABIST_SCHED_EN ="1", ABIST runs indefinitely with cycle time determined by ABIST_SCHED_DLY and it is stopped when ABIST_GROUPx_START bit is cleared.

The number of ABIST groups of tests depends on how many ABIST_GROUPx_START bits have been set while the ABIST_SCHED_EN configuration bit in the SAFETY_CFG2 register is not set. The options are four ABIST group of tests (or a full ABIST run), three ABIST group of tests, two ABIST group of tests, or just one ABIST group of tests. Examples of the different groups of tests include any of the following:

  • ABIST Group 1 → ABIST Group 2 → ABIST Group 3 → ABIST Group 4, or
  • ABIST Group 1 → ABIST Group 2 → ABIST Group 3, or
  • ABIST Group 1 → ABIST Group 3 → ABIST Group 4, or
  • ABIST Group 2 → ABIST Group 3 → ABIST Group 4, or
  • ABIST Group 1 → ABIST Group 2, or
  • ABIST Group 1 → ABIST Group 3, or
  • ABIST Group 1 → ABIST Group 4, or
  • ABIST Group 2 → ABIST Group 3, or
  • ABIST Group 2 → ABIST Group 4, or
  • ABIST Group 3 → ABIST Group 4, or
  • ABIST Group 1, or
  • ABIST Group 2, or
  • ABIST Group 3, or
  • ABIST Group 4

The full ABIST run, when the device is in the DIAGNOSTIC or ACTIVE state, includes a diagnostic check of the error monitor for the ENDRV/nIRQ output driver by allowing comparators in the overtemperature monitors (ABIST Group 4) to toggle the ENDRV/nIRQ pin in a known pattern for the duration of an analog comparator test, if any of the BUCKx/BOOST_OT_WARN_IRQ_EN bits are set. The ABIST of the overtemperature monitors includes both the warning and shutdown comparators. When the device is in the SAFE state, the ENDRV/nIRQ pin is always pulled to logic 0.

The diagnostics of the error monitor for the NRES output driver is performed by the LBIST.

At any time when an ABIST group of tests is set to run, the ABIST tests are activated only during the analog comparator output steady state (sampled analog comparator output matches respective deglitched output and SPI status bit).

If none of these conditions are met, then initiation of an ABIST run is delayed. The maximum wait time of an ABIST start is limited by its ABIST time-out function, which is ≈112 µs.

The full ABIST run is activated by setting all four ABIST_GROUPx_START control bits in the SAFETY_ABIST_CTRL register. As each ABIST group of tests are complete, a corresponding ABIST_GROUPx_DONE status bit is set in the SAFETY_ABIST_ERR_STAT1 status register. This ABIST_GROUPx_DONE status bit is cleared when the corresponding ABIST group of tests are running and is set to 1b when the corresponding ABIST group of tests are complete.

If any of scheduled diagnostic tests fail during an ABIST run or an ABIST time-out occurs and the ABIST_ACTIVE_FAIL_RESP bit is set to 0b, then the following occurs:

  • The device goes into the SAFE state.
  • One or more ABIST error status bits in the SAFETY_ABIST_ERR_STAT1 through
    the SAFETY_ABIST_ERR_STAT6 registers are set.
  • The ENDRV/nIRQ pin is asserted low to interrupt the external system MCU.

This enables an interrupting of the external MCU in case of a detected ABIST failure and confirms its root cause by reading the SAFETY_ABIST_ERR_STAT1 through the SAFETY_ABIST_ERR_STAT6 status registers.

If any of the scheduled diagnostic tests fail during an ABIST run or an ABIST time-out occurs, and the ABIST_ACTIVE_FAIL_RESP bit is set to 1b, then the following occurs:

  • The device does not change state.
  • One or more ABIST error status bits in the SAFETY_ABIST_ERR_STAT1 through
    the SAFETY_ABIST_ERR_STAT6 registers are set.

Undervoltage and overvoltage comparator diagnostic tests do not impact the regulated output-voltage rails. This ABIST run does not include a circuit check of the regulator current-limit, VREG UV and VREG OV, and VIN UV and VIN OV diagnostic checks. When the VREG regulator is enabled, running the VREG UV and VREG OV diagnostics causes the VREG output to become uncontrollable, and for that reason it is excluded from this ABIST run.

GUID-67FBFC86-5F6A-466C-9137-7816162AAAD6-low.gif Figure 11-8 ABIST Delayed Test Pulses

In the DIAGNOSTIC and SAFE state, the time interval, t2 (time delay measured from the falling edge of test pulse n and the next rising edge of test pulse n+1), is a couple of system clock cycles.

GUID-2D2E6EAD-1B51-4542-A22C-29AC08E635BD-low.gif
  1. ENDRV toggling is checked by the system MCU.
Figure 11-9 Full ABIST When the Device is in the DIAGNOSTIC, ACTIVE, or SAFE State

Figure 11-10 shows an example for running only the tests for the ABIST Group 1 and ABIST Group 4 groups by setting the ABIST_GROUP1_START and ABIST_GROUP42_START control bits in the
SAFETY_ABIST_CTRL register.

GUID-2C8C30C3-4CD3-4702-BDFD-F15F393BC66C-low.gif
  1. ENDRV toggling is checked by the system MCU.
Figure 11-10 Partial ABIST Run When the Device is in the DIAGNOSTIC, ACTIVE, or SAFE State