SLVSBO3A December   2013  – December 2015 TPS657120

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: General Functions
    6. 4.6  Electrical Characteristics: DCDC1 and DCDC2
    7. 4.7  Electrical Characteristics: DCDC3
    8. 4.8  Electrical Characteristics: RF-LDOs
    9. 4.9  Electrical Characteristics: Digital Inputs, Digital Outputs
    10. 4.10 Electrical Characteristics: Thermal Shutdown, Undervoltage Lockout
    11. 4.11 Electrical Characteristics: RFFE Timing Parameters
    12. 4.12 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Default Settings
      2. 5.3.2  Linear Regulators
        1. 5.3.2.1 Low Quiescent Current (Eco) Mode
        2. 5.3.2.2 Output Discharge
        3. 5.3.2.3 LDO Enable
        4. 5.3.2.4 LDO Voltage Range
        5. 5.3.2.5 LDO Power Good Comparator
      3. 5.3.3  Step-down Converters DCDC1 and DCDC2
      4. 5.3.4  Power Save Mode
      5. 5.3.5  Dynamic Voltage Positioning (Optional)
      6. 5.3.6  Soft Start / Enable
      7. 5.3.7  Dynamic Voltage Scaling (DVS) for DCDC1, DCDC2 and DCDC3
      8. 5.3.8  100% Duty Cycle Low Dropout Operation
      9. 5.3.9  180° Out-of-Phase Operation
      10. 5.3.10 Undervoltage Lockout for DCDC1, DCDC2, DCDC3, LDO1 and LDO2
      11. 5.3.11 Output Voltage Discharge
      12. 5.3.12 Short-Circuit Protection
      13. 5.3.13 Output Voltage Monitoring
      14. 5.3.14 Step-Down Converter and LDO Enable; pins CLK_REQ1 and CLK_REQ2
      15. 5.3.15 Step-Down Converter DCDC3
      16. 5.3.16 DCDC3_SEL Control
        1. 5.3.16.1 DCDC3_SEL Control - Voltage Mapping Option
        2. 5.3.16.2 DCDC3_SEL Control - Mapping the Enable Signal for the Negative Current Limit of DCDC3 to DCDC3_SEL; Additional Option for Rev 1.1 and Higher Only
      17. 5.3.17 Bypass Switch
      18. 5.3.18 DCDC3 Output Voltage Ramp Support
      19. 5.3.19 VCON Decoder
      20. 5.3.20 Thermal Monitoring and Shutdown
      21. 5.3.21 GPIOs
      22. 5.3.22 nRESET Input ; ADR_SELECT Input
      23. 5.3.23 Power State Machine
      24. 5.3.24 Implementation of Internal Power-Up and Power-Down Sequencing
      25. 5.3.25 VDDIO Voltage for Push-pull Output Stages / Interface
      26. 5.3.26 TPS657120 On Off Operation
        1. 5.3.26.1 TPS657120 Power-Up
        2. 5.3.26.2 TPS657120 PWR_REQ Driving DCDC1, DCDC2 and LDO1
      27. 5.3.27 MIPI RFFE Interface
        1. 5.3.27.1 MIPI RFFE Write Cycle
        2. 5.3.27.2 MIPI RFFE Read Cycle
    4. 5.4 Device Functional Modes
    5. 5.5 Register Maps
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 6.2.2.1.1 Inductor Selection
          2. 6.2.2.1.2 Output Capacitor Selection
          3. 6.2.2.1.3 Input Capacitor / Output Capacitor Selection
          4. 6.2.2.1.4 Voltage Change on DCDC1, DCDC2 and DCDC3
      3. 6.2.3 Application Curve
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

6.1 Application Information

The target application is powering a Baseband and RF-PA.

6.2 Typical Application

TPS657120 TPS65712_application_5x6.gif Figure 6-1 Phone Battery Connections for SP30 RF PMIC

6.2.1 Design Requirements

The design requirements are shown in Table 6-1.

Table 6-1 Design Parameters

DESIGN PARAMETER VALUE
Typical Input Voltage 5.0 V
DCDC1 Output Voltage 1.7 V
DCDC2 Output Voltage 2.65 V
DCDC3 Output Voltage 3.8 V
LDO1 Output Voltage 1.8 V
LDO2 Output Voltage 2.8 V

6.2.2 Detailed Design Procedure

6.2.2.1 Output Filter Design (Inductor and Output Capacitor)

6.2.2.1.1 Inductor Selection

The converters operates typically with a 1.5-µH or 2.2-µH output inductor. The selected inductor has to be rated for its dc resistance and saturation current. The DC resistance of the inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest dc resistance should be selected for highest efficiency.

Equation 1 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 1. This is recommended because during heavy load transient the inductor current will rise above the calculated value.

Equation 1. TPS657120 EQ1_DIL_lvsae1.gif

where

  • f = Switching Frequency (2.25MHz typical)
  • L = Inductor Value
  • ΔIL = Peak-to-Peak inductor ripple current
  • ILmax = Maximum Inductor current

The highest inductor current will occur at maximum Vin.

Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. It must be considered, that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies.

Note that the step down converter has internal loop compensation. The internal loop compensation is designed to work with an output filter corner frequency calculated as follows:

Equation 2. TPS657120 EQ2_fc_lvsae1.gif

This leads to the fact the selection of external L-C filter has to be coped with the above equation. As a general rule the product of L x COUT should be constant while selecting smaller inductor or increasing output capacitor value.

Refer to Table 6-2 and the typical applications for possible inductors.

Table 6-2 Tested Inductors

INDUCTOR TYPE INDUCTOR VALUE SUPPLIER COMMENT
MDT1608-CH2R2M 2.2 µH Toko for DCDC1 and DCDC2 (small size)
MDT2012-CH2R2N 2.2 µH Toko for DCDC1 and DCDC2 (small size, good efficiency)
DFE201610C-2R2 2.2 µH Toko for DCDC1 and DCDC2 (high efficiency)
DFE252010-1R5N 1.5 µH Toko for DCDC3

6.2.2.1.2 Output Capacitor Selection

The advanced Fast Response voltage mode control scheme of the step-down converter allows the use of small ceramic capacitors with a typical value of 10 µF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are therefore recommended. For an inductor value of 1.5 µH or 2.2 µH, an output capacitor with 10 µF can be used. See the recommended components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. Just for completeness the RMS ripple current is calculated using Equation 3.

Equation 3. TPS657120 EQ3_Irms_lvsae1.gif

At nominal load currents, the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor; see Equation 4.

Equation 4. TPS657120 EQ4_Dvout_lvsae1.gif

Where the highest output voltage ripple occurs at the highest input voltage Vin.

At light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.

6.2.2.1.3 Input Capacitor / Output Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The converters need a ceramic input capacitor of 10 μF. The input capacitor can be increased without any limit for better input voltage filtering. As the output capacitor influences the loop stability, any deviation form the required output capacitance may cause the DC-DC converter or LDO to become unstable.

Table 6-3 Tested Capacitors

TYPE VALUE VOLTAGE RATING SIZE SUPPLIER MATERIAL
GRM155R60J475ME87 4.7 µF 6.3 V 0402 Murata Ceramic X5R
GRM155R60J225ME15D 2.2 µF 6.3 V 0402 Murata Ceramic X5R
GRM185R60J225 2.2 µF 6.3 V 0603 Murata Ceramic X5R
GRM188R60J475KE19 4.7 µF 6.3 V 0603 Murata Ceramic X5R
GRM188R61A106ME69 10 µF 10 V 0603 Murata Ceramic X5R
GRM21BR60J226M 22 μF 6.3 V 0805 Murata Ceramic X5R
GRM21BR60J476ME15 47 μF 6.3 V 0805 Murata Ceramic X5R

6.2.2.1.4 Voltage Change on DCDC1, DCDC2 and DCDC3

The output voltage of the DC-DC converters can be changed during operation by the digital interface. In addition, the DC-DC converters can be configured such that toggling DCDC3_SEL switches between two different sets of output voltages defined in registers DCDCx_OP and DCDCx_AVS.

6.2.3 Application Curve

TPS657120 Scope_17_SLVSBO3.gif