5.3.1 Default Settings

See Table 5-1 for the default output voltages for the DCDC converters and the LDOs. For DCDC1 to DCDC3 and LDO1 and LDO2, there are two registers defining the output voltage. DCDC3_SEL allows to switch in between the two output voltages defined in the _OP and _AVS register of DCDC3. For the other DCDC converters and LDOs, switching is possible by a register Bit.

5.3.2 Linear Regulators

The power management core has 2 high PSRR, low noise LDOs with different output current capabilities. Each LDO output voltage can be set independently through the communication bus (see Table 5-19) and the transition occurs immediately if the LDO is enabled.

5.3.3 Step-down Converters DCDC1 and DCDC2

The TPS657120 step down converters operate with typically 2.25-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. With DCDCx_MODE bit set to 0, at light load currents the converter can automatically enter Power Save Mode and operates then in PFM mode.

During PWM operation the converter uses a unique fast response voltage mode control scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is turned on. The current flows now from the input capacitor via the High Side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current limit of the High Side MOSFET switch is exceeded. After an off time preventing shoot through current, the Low Side MOSFET rectifier is turned on and the inductor current will ramp down. The current flows now from the inductor to the output capacitor and to the load. It returns back to the inductor through the Low Side MOSFET rectifier.

The next cycle is initiated by the clock signal again turning off the Low Side MOSFET rectifier and turning on the on the High Side MOSFET switch. A 180° phase shift between DCDC1 and DCDC2 decreases the input RMS current and synchronizes the operation of the two dcdc converts. The feedback pin (VDCDCx) must directly be connected to the output voltage of the DCDC converter and no external resistor network must be connected.

5.3.4 Power Save Mode

The Power Save Mode is enabled with the DCDCx_MODE bit set to 0. If the load current decreases, the converter will enter Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically +1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the Low Side MOSFET switch becomes zero, which indicates discontinuous conduction mode. During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT nominal +1%, the device starts a PFM current pulse. The High Side MOSFET switch will turn on, and the inductor current ramps up. After the On-time expires, the switch is turned off and the Low Side MOSFET switch is turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current, the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical 25-µA current consumption.

If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold. With a fast single threshold comparator, the output voltage ripple during PFM mode operation can be kept small. The PFM Pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. Increasing output capacitor values and inductor values will minimize the output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode is entered in case the output current can not longer be supported in PFM mode. The Power Save Mode can be disabled by setting Mode pin to high. The converter will then operate in fixed frequency PWM mode.

5.3.5 Dynamic Voltage Positioning (Optional)

This feature reduces the voltage under/overshoots at load steps from light to heavy load and heavy to light. It is active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. Dynamic voltage positioning is an optional feature set at TI and can be enabled / disabled on request.

5.3.6 Soft Start / Enable

Step-Down converter ENABLE

The step-down converter enable/disable is part of the flexible power-up and power-down state machine. Each converter can be programmed such that it is powered up automatically in one of the 15 time slots after a power-on condition occurs or is controlled by a dedicated pin. Pins CLK_REQ1 and CLK_REQ2 can be mapped to any resource (LDOs, dcdc converter) to enable or disable it.

Step-Down converter SOFT START

The step-down converters in TPS657120 have an internal soft start circuit that controls the ramp up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within a time defined in the electrical spec. This limits the inrush current in the converter during start up and prevents possible input voltage drops when a battery or high impedance power source is used. The Soft start circuit is enabled after the start up time t_Start has expired. For DCDC3, there is an option to set two different values for the start-up and ramp-time. For applications that require a fast response, set DCDC3_CTRL:RAMP_TIME = 1.

During soft start, the output voltage ramp up is controlled as shown in Figure 5-1.

Figure 5-1 Soft Start

5.3.7 Dynamic Voltage Scaling (DVS) for DCDC1, DCDC2 and DCDC3

The DCDC converters in TPS657120 allow to change the output voltage during operation by changing the register content or by switching between the settings defined by DCDCx_OP and DCDCx_AVS registers. Switching between DCDCx_OP and DCDCx_AVS registers is done by pin DCDC3_SEL. The name indicates that the pin is used for DCDC3 exclusively but DCDC1 and/or DCDC2 could be mapped to the pin same as DCDC3 to change in between two different output voltages by toggling the pin. Mapping of the voltage scaling function is done by DCDCx_CTRL registers bit DCDCx_SEL_CTRL for each of the converters. When a change in output voltage occurs, the new voltage will be ramped to either immediately if DCDCx_CTRL:IMMEDIATE=1 or the slew rate defined by DCDCx_CTRL:TSTEP with the IMMEDIATE bit set to 0. The slew rate control is implemented such that TSTEP defines the time from one output voltage step to the next, stepping through all steps until the new target is reached. While the voltage change is active, the converter is forced to PWM mode to allow defined rise and fall times of the output voltage. DVS is not active for DCDC3 when operated in VCON mode but the converter will follow the analog signal at VCON.

The DVS state machine which ramps the output voltage to the target within the programmed time is automatically disabled when a converter is disabled. Therefore a voltage change will only be processed if the converter is active. If a converter is being disabled, the target voltage in the register now is changed with a certain TSTEP setting and the converter is enabled, the DVS will start to ramp to the target. For the two slowest TSSTEP settings, the 130-µs initial enable delay of a converter will not be long enough to cover that ramp time. This will result in a voltage, still ramping to the new target during power-up.

5.3.8 100% Duty Cycle Low Dropout Operation

The device starts to enter 100% duty cycle mode once the input voltage comes close to the nominal output voltage. In order to maintain the output voltage, the High Side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN the High Side MOSFET switch is turned on completely. In this case, the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated with Equation 1.

5.3.9 180° Out-of-Phase Operation

In PWM Mode, the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths the input current. This feature reduces the surge current drawn from the supply.

5.3.10 Undervoltage Lockout for DCDC1, DCDC2, DCDC3, LDO1 and LDO2

The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the DC-DC converters and LDOs at too low input voltages. See the electrical characteristics for the undervoltage lockout threshold voltage.

5.3.11 Output Voltage Discharge

The dcdc converters and LDOs contain an output capacitor discharge feature which makes sure that the capacitor is discharged when the dcdc converter or LDO is disabled.

5.3.12 Short-Circuit Protection

All outputs are short circuit protected with a maximum output current as defined in the electrical specifications.

5.3.13 Output Voltage Monitoring

Internal power good comparators monitors the switching regulator outputs and detect when the output voltage is below the target value. This information is used by the power management core to set and clear the power good Bits in the register set accordingly. A switching regulator’s individual power good comparator will be blanked when the regulator is disabled or when the regulator’s voltage is transitioning from one set point to another.

5.3.14 Step-Down Converter and LDO Enable; pins CLK_REQ1 and CLK_REQ2

The step-down converter and LDO enable/disable is part of the flexible power-up and power-down state machine. Each converter can be programmed such that it is powered up automatically at the beginning of on out of 8 time slots after a power-on condition occurs. Alternatively, a resource can be mapped to a dedicated pin controlling the enable function. Pins CLK_REQ1 and CLK_REQ2 serve this function for any resource (LDO, DCDC converter) to enable or disable it. As long as a resource is not mapped to a pin, the enable bit defines the status. If a resource is mapped to a pin, the status of the enable bit is ignored and the pin controls the enable function.

As soon as a resource is mapped to the CLK_REQ1 pin and there is a falling edge on that pin, all _OP and _AVS registers (for all resources) are re-loaded to their OTP default settings. For Rev 1.0 of silicon the default settings were loaded based on a falling edge of either one of the CLK_REQ pins. During the 25us it takes to re-load the registers, the RFFE interface is in reset and no communication is possible. The RFFE interface is also held in reset during a 2.5-µs period after a rising edge of the CLK_REQx pins. CLK_REQ mapping should be done with a 2-µs setup time; for example, CLK_REQ pins shall have a stable, high-level 2 µs before the pin is mapped for a converter which is on by default.

5.3.15 Step-Down Converter DCDC3

DCDC3 is intended to be used as the power supply for a RF- power amplifier (RF-PA). Its output current of up to 2.5A allows operation with 2G / 3G and 4G amplifiers. There are two different operating modes with respect to how the output voltage is set:

• by registers DCDC3_OP or DCDC3_AVS used for 3G/4G; the output voltage range is 0.8 V to 3.8 V; PWM/PFM mode allowed
• by analog signal at pin VCON used for 2G optionally; the output voltage range is 0.1 V to 3.8 V; forced PWM mode only; see details under VCON DECODER

Pin DCDC3_SEL can be mapped to any of the 3 step-down converters but typically is used for DCDC3 only. It allows to switch in between the voltage setting based on DCDC3_OP and DCDC3_AVS. Each, DCDC3_OP and DCDC3_AVS contain the Bits to set the output voltage of DCDC3, force PWM mode and also open/close the BYPASS switch.

5.3.16 DCDC3_SEL Control

5.3.17 Bypass Switch

There is a bypass switch for DCDC3 with the input pins shared between the bypass switch and the power stage of the step-down converter. The switch is driven manually depending on the settings of EN_BYPASS defined in register DCDC3_OP and DCDC3_AVS.

There is a overvoltage protection (OVP) with a 4.0-V threshold sensed at the output of DCDC3 to protect the RF-PA powered by DCDC3 for cases where the bypass switch is closed and the supply voltage from an unregulated charger / power path is rising immediately to 5 V. In this case, the bypass switch is forced to open independent of setting of EN_BYPASS. Bit DCDC_CONTROL:DCDC3_OVP is set to 1 in an OVP event and needs to be cleared in software in order to close the bypass switch again using EN_BYPASS.

When the bypass switch is closed, PWM mode of DCDC3 is blocked and its high side switch is forced ON.

5.3.18 DCDC3 Output Voltage Ramp Support

There is circuitry to ensure a fast output voltage change on DCDC3. This is accomplished by automatically enabling the bypass switch to support a ramp of DCDC3 to higher output voltages independent of the setting of EN_BYPASS. In an OVP event, when DCDC3_OVP is set, the ramp support is disabled and bit DCDC3_OVP has to be cleared for proper operation of the ramp support circuit. In addition, the ramp support can be disabled by clearing DCDC3_EN_UP. In addition, there is a down ramp support which ensures fast down-ramping of DCDC3. That function can be disabled independently from the up-ramping support by DCDC3_EN_DWN and is not affected by the status of the OVP.

From Rev 1.1 of silicon bits DCDC3_S2 and DCDC3_S1 have been added to register DCDC_CONFIG1. The bits allow to change the threshold for the ramp support circuit and therefore allow to adjust the shape of the rising edge of the output voltage during a VCON transition.

There are a couple of register bits to control the function of the ramp support as listed below.

• DCDC_CONFIG:DCDC3_EN_UP: enables the ramp support for rising VCON / output voltages
• DCDC_CONFIG:DCDC3_EN_DWN: enables the ramp support for falling VCON / output voltages
• DCDC_CONFIG:DCDC3_DWN_2X: doubles the current in the ramp down circuit to speed up the down slope
• DCDC_CONFIG:DCDC3[S2:S1]: define the threshold below the nominal output voltage when the ramp support stops supporting
• SPARE0:EN_nILIM_xl: enables or disables the negative current limit in DCDC3; a large current limit speeds up the falling edge of Vout
• SPARE0:EN_FAST_RAMP: rising edge of Vout is further speed up; it is recommended to keep this bit cleared as it may cause overshoot when set

The ramp-up and ramp-down support circuitry is intended to be used during GMSK ramping with the VCON input driven to define the output voltage of DCDC3. It is recommended to keep the ramp support disabled when the DCDC3 converter is not operated in VCON mode (when DCDC3_CTRL:VCON=0).

5.3.19 VCON Decoder

The VCON decoder allows to control the output voltage of DCDC3 by an analog signal to pin VCON. The gain and offset of the VCON decoder can be adjusted by register VCON. Typically it will be driven with an input voltage in the range of 0 mV (or 200 mV) to 2100 mV. In VCON operation, DCDC3 is forced to fixed frequency PWM operation independent of the setting of DCDC3_MODE in register DCDC3_OP or DCDC3_AVS. In addition, the converter is forced to be enabled with VCON=1 independent of the status of the ENABLE bit or status of the CLK_REQ signals if mapped.

The gain and offset settings are listed in the register description for the VCON register. DCDC3 ramp support is used also in VCON mode to ensure a fast transition of the output voltage.

The output voltage of DCDC3 in VCON mode is defined using Equation 2.

With a typical output voltage range at DCDC3 of 100 mV to 3.5 V, the default gain and offset settings are:

• gain: 1.8
• Voffset: –250 mV

5.3.20 Thermal Monitoring and Shutdown

The is a thermal protection module that monitors the junction temperature of the device.

When the Thermal Shutdown temperature threshold is reached the TPS657120 is set under reset and a transition to STANDBY state is initiated. The POWER ON enable conditions of the device will not be taken into consideration until the die temperature has decreased below the Thermal Shutdown threshold.

The thermal protection is enabled in ACTIVE state. The thermal protection is automatically enabled during an STANDBY to ACTIVE state transition and will be kept enabled in STANDBY state after a switch-off sequence caused by a thermal shutdown event. Recovery from this STANDBY state will be initiated (switch-on sequence) when the die temperature will fall below the Thermal Shutdown temperature threshold. In a thermal event, all resources are powered down at the same time.

5.3.21 GPIOs

There are 2 GPIOs in TPS657120. If the output stage is programmed to push-pull, it pulls to the high-voltage set by VDDIO. With VDDIO being below the VDDIO undervoltage lockout, the high side driver is disabled and the output is set to open drain. The default state of the GPIO is defined as an output with state LOW. In addition, the GPIOs allow to add an internal 4.7-kΩ pulldown resistor optionally.

A GPIO can alternatively be programmed such that it is assigned to the power-up sequencing by setting GPIO_CFG=1. In this case the GPIO output will be set according to the definition in GPIOx:GPIO_SET during one of the 8 time slots as defined by internal power-up sequencing.

Figure 5-2 GPIO block

5.3.22 nRESET Input ; ADR_SELECT Input

GPIO0 and GPIO1 can optionally be assigned as nRESET input or ADR_SELECT input defining the USID[0] bit as defined in the register description. The alternative function is selected by a bit in the GPIOx register as described as follows:

Detailed description for GPIO0 (nRESET):

• GPIO0:nRESET=0: The pin is used as a GPIO based on OTP programming. However, in reset state, before internal OTP is read, the pin defaults to an nRESET input, so the pin has to be pulled to a logic HIGH per default in order to exit reset and load OTP, reconfiguring it as GPIO.
• GPIO0:nRESET=1 (default OTP setting): The pin is used as an active low reset input. The pin needs to be pulled to logic HIGH externally to exit reset and allow TPS657120 going to standby state. With GPIO0:nRESET=1, the pin is automatically configured as an input independent of setting of GPIO0:GPIO_CFG.

Detailed description for GPIO1 (ADR_SELECT):

• GPIO1:ADR_SELECT=0:The pin is used as a GPIO
• GPIO1:ADR_SELECT=1 (default OTP setting): The pin defaults to GPIO and is reprogrammed to an address select bit once internal OTP is read in the boot phase. With GPIO1:ADR_SEL=1, the pin is automatically configured as an input independent of setting of GPIO1:GPIO_CFG. A status change on pin ADR_SELECT will become effective immediately, so USID[0] can be updated at any time by changing the pin status.

5.3.23 Power State Machine

The Embedded Power Controller (EPC) manages the state of the device and controls the power up sequence.

The EPC will support the following states:

• NO SUPPLY: The main battery supply voltage is not high enough to power the internal LDO and bandgap. Everything on the device is off.
• BOOT PHASE (READ OTP): The internal supply and bandgap are active and the device is reading its configuration data out of OTP memory.
• STANDBY: The internal supply and bandgap are active, register default settings have been loaded and the device is waiting for PWRON going HIGH to start the power-up sequence
• ACTIVE: Device POWER ON enable conditions are met and regulated power supplies are ON or can be enabled with full current capability. Reset is released; interfaces are active

5.3.24 Implementation of Internal Power-Up and Power-Down Sequencing

TPS657120 allows to internally enable resources during power-up (going from STAND-BY to ACTIVE state) and power-down (going from ACTIVE to STANDBY state) . The internal power-sequencing is defined in OTP memory programmed at TI. The sequencing allows to enable resources in 8 time slots during power-up and power-down. A resource can be associated to any of these 8 time slots that will be processed in the opposite direction during power-down. The delay in between the time slots is fixed to 500 µs.

Resources may include:

• step-down converters
• LDOs
• GPIOs

Resources that are not part of the automatic sequencing may be configured such that they are enabled by external pins or by their enable Bit in the register set. See STEP-DOWN CONVERTER ENABLE

5.3.25 VDDIO Voltage for Push-pull Output Stages / Interface

Push-pull output stages are pulled HIGH to the voltage applied at pin VDDIO for the pins listed below:

• SDATA
• GPIO0,1: push-pull only

The signal levels on the interface pins SDATA and SCLK are on VDDIO level. No voltage must be applied exceeding the voltage level at VDDIO.

5.3.26 TPS657120 On Off Operation

The power-up sequencing in TPS657120 is flexible and can be set such that it allows to power up the converters and LDOs in any order with the down-sequencing being the reverse or all converters and LDOs powering down at the same time.

5.3.26.1 TPS657120 Power-Up

If PWRON is tied to the supply voltage so TPS65712 starts its power-up sequencing once the input voltage is above the UVLO threshold and the internal boot phase is finished.

Figure 5-3 TPS657120 Power-Up

5.3.26.2 TPS657120 PWR_REQ Driving DCDC1, DCDC2 and LDO1

Once the CLK_REQ1 and CLK_REQ2 pins are enabled to take control of DCDC1, DCDC2 and LDO1, these converters/LDO are enabled if either one of the pins is driven HIGH.

Figure 5-4 TPS657120 Power Cut

5.3.27 MIPI RFFE Interface

There is a MIPI RFFE compatible interface based on the Rev 1.00.00 specification. The interface is only active in ACTIVE state of TPS657120 - see the power-up timing diagram. RFFE communication is not possible when the _OP and _AVS register are reloaded triggered by a falling edge on CLK_REQx once any DCDC converter or LDO is mapped to that pin. During the 25 µs of re-loading the registers with the OTP content, the RFFE interface is held in reset. The RFFE interface is also held in reset during a 2.5-µs period after a rising edge of the CLK_REQx pins. The slave address bits SA3...SA0 are equivalent to the unique slave identifier (USID) defined in the MIPI RFFE specification. As defined in the RFFE specification, the bits are located in register USID along with the other RFFE-pre-defined registers PM_TRIG, PRODUCT_ID and MANUFACTURER_ID at address 0x1C to 0x1F.

5.3.27.1 MIPI RFFE Write Cycle

Figure 5-5 RFFE Write Cycle

5.3.27.2 MIPI RFFE Read Cycle

Figure 5-6 RFFE Read Cycle

Table 5-2 DCDC1_CTRL⁽¹⁾; Register Address: 00h

Table 5-3 DCDC2_CTRL⁽¹⁾; Register Address: 01h

Table 5-4 DCDC3_CTRL⁽¹⁾; Register Address: 02h

Table 5-5 DCDCx TSTEP Settings

Table 5-6 DCDC1_OP⁽¹⁾; Register Address: 03h

Table 5-7 DCDC1_AVS⁽¹⁾; Register Address: 04h

Table 5-8 DCDC2_OP⁽¹⁾; Register Address: 05h

Table 5-9 DCDC2_AVS⁽¹⁾; Register Address: 06h

Table 5-10 DCDC3_OP⁽¹⁾; Register Address: 07h

Table 5-11 DCDC3_AVS⁽¹⁾; Register Address: 08h

Table 5-12 VCON⁽¹⁾; Register Address: 09h

Table 5-13 VCON Gain Settings

Table 5-14 VCON Offset Settings

Table 5-15 DCDC1 and DCDC2 Voltage Settings

Table 5-16 DCDC3 Voltage Settings

Table 5-17 LDO_CTRL⁽¹⁾; Register Address: 0Ah

LDO1_OP⁽¹⁾; Register Address: 0Bh

Table 5-18 LDO2_OP⁽¹⁾; Register Address: 0Ch

Table 5-19 LDO Voltage Settings

Table 5-20 DEVCTRL⁽¹⁾; Register Address: 0Dh

Table 5-21 DISCHARGE⁽¹⁾; Register Address: 0Eh

Table 5-22 PGOOD⁽¹⁾; Register Address: 0Fh

Table 5-23 GPIO0⁽¹⁾; Register Address: 10h

Table 5-24 GPIO1⁽¹⁾; Register Address: 11h

Table 5-25 DCDC_CONFIG1⁽¹⁾ ; Register Address: 12h

Table 5-26 DCDC_CONFIG2⁽¹⁾ ; Register Address: 13h

Table 5-27 SPARE0⁽¹⁾ ; Register Address: 14h

Table 5-28 VERNUM⁽¹⁾ ; Register Address: 15h

Table 5-29 PM_TRIG⁽¹⁾ ; Register Address: 1Ch; function not supported by TPS657120

Table 5-30 PRODUCT_ID⁽¹⁾ ; Register Address: 1Dh

Table 5-31 MANUFACTURER_ID⁽¹⁾ ; Register Address: 1Eh

Table 5-32 USID⁽¹⁾ ; Register Address: 1Fh