SLIS165G December   2014  – February 2019 TPS659037

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1.     Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Latch Up Rating
    6. 4.6  Electrical Characteristics: LDO Regulator
    7. 4.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 4.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 4.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 4.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 4.11 Electrical Characteristics: DC-DC Clock Sync
    12. 4.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 4.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 4.14 Electrical Characteristics: System Control Threshold
    15. 4.15 Electrical Characteristics: Current Consumption
    16. 4.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 4.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 4.18 Electrical Characteristics: I/O Pullup and Pulldown
    19. 4.19 I2C Interface Timing Requirements
    20. 4.20 SPI Timing Requirements
    21. 4.21 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Power Management
      2. 5.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 5.3.2.1 Step-Down Regulators
          1. 5.3.2.1.1 Sync Clock Functionality
          2. 5.3.2.1.2 Output Voltage and Mode Selection
          3. 5.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 5.3.2.1.4 POWERGOOD
          5. 5.3.2.1.5 DVS-Capable Regulators
          6. 5.3.2.1.6 Non DVS-Capable Regulators
          7. 5.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 5.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 5.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 5.3.2.2 LDOs – Low Dropout Regulators
          1. 5.3.2.2.1 LDOVANA
          2. 5.3.2.2.2 LDOVRTC
          3. 5.3.2.2.3 LDO Bypass (LDO9)
          4. 5.3.2.2.4 LDOUSB
          5. 5.3.2.2.5 Other LDOs
      3. 5.3.3  Long-Press Key Detection
      4. 5.3.4  RTC
        1. 5.3.4.1 General Description
        2. 5.3.4.2 Time Calendar Registers
          1. 5.3.4.2.1 TC Registers Read Access
          2. 5.3.4.2.2 TC Registers Write Access
        3. 5.3.4.3 RTC Alarm
        4. 5.3.4.4 RTC Interrupts
        5. 5.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 5.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 5.3.5.1 Asynchronous Conversion Request (SW)
        2. 5.3.5.2 Periodic Conversion Request (AUTO)
        3. 5.3.5.3 Calibration
      6. 5.3.6  General-Purpose I/Os (GPIO Pins)
        1. 5.3.6.1 REGEN Output
      7. 5.3.7  Thermal Monitoring
        1. 5.3.7.1 Hot-Die Function (HD)
        2. 5.3.7.2 Thermal Shutdown (TS)
        3. 5.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 5.3.8  Interrupts
      9. 5.3.9  Control Interfaces
        1. 5.3.9.1 I2C Interfaces
          1. 5.3.9.1.1 I2C Implementation
          2. 5.3.9.1.2 F/S Mode Protocol
          3. 5.3.9.1.3 HS Mode Protocol
        2. 5.3.9.2 Serial-Peripheral Interface (SPI)
          1. 5.3.9.2.1 SPI Modes
          2. 5.3.9.2.2 SPI Protocol
      10. 5.3.10 Device Identification
    4. 5.4 Device Functional Modes
      1. 5.4.1  Embedded Power Controller
      2. 5.4.2  State Transition Requests
        1. 5.4.2.1 ON Requests
        2. 5.4.2.2 OFF Requests
        3. 5.4.2.3 SLEEP and WAKE Requests
      3. 5.4.3  Power Sequences
      4. 5.4.4  Startup Timing and RESET_OUT Generation
      5. 5.4.5  Power On Acknowledge
        1. 5.4.5.1 POWERHOLD Mode
        2. 5.4.5.2 AUTODEVON Mode
      6. 5.4.6  BOOT Configuration
        1. 5.4.6.1 Boot Pin Selection
      7. 5.4.7  Reset Levels
      8. 5.4.8  Warm Reset
      9. 5.4.9  RESET_IN
      10. 5.4.10 Watchdog Timer (WDT)
      11. 5.4.11 System Voltage Monitoring
        1. 5.4.11.1 Generating a POR
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1  Recommended External Components
        2. 6.2.2.2  SMPS Input Capacitors
        3. 6.2.2.3  SMPS Output Capacitors
        4. 6.2.2.4  SMPS Inductors
        5. 6.2.2.5  LDO Input Capacitors
        6. 6.2.2.6  LDO Output Capacitors
        7. 6.2.2.7  VCC1
          1. 6.2.2.7.1 Meeting the Power Down Sequence
          2. 6.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 6.2.2.8  VIO_IN
        9. 6.2.2.9  16-MHz Crystal
        10. 6.2.2.10 GPADC
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.6.1 REGEN Output

Dedicated REGEN signal REGEN1 can be programmed to be part of power sequences to enable external devices like external SMPS. The REGEN2 signal is MUXed in GPIO_2, and when REGEN2 mode is selected it can also be programmed to be part of power sequences. All REGEN signals are at VSYS level.