SWCS095L August 2013 – February 2019 TPS659038-Q1 , TPS659039-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Table 6-6 lists the TPS65903x-Q1 interrupts.
These interrupts are split into four register groups (INT1, INT2, INT3, INT4) and each group has three associated control registers:
The INT4 register group has two additional registers, INT4_EDGE_DETECT1 and
INT4_EDGE_DETECT2, to independently configure rising and falling edge detection.
All interrupts are logically combined on a single output line INT (default active low). This line is used as an external interrupt line to warn the host processor of any interrupt event that has occurred within the device. The host processor has to read the interrupt status registers (INTx_STATUS) through the control interface (I2C or SPI) to identify the interrupt source(s). Any interrupt source can be masked by programming the corresponding mask register (INTx_MASK). When an interrupt is masked, its associated event detection mechanism is disabled. Therefore the corresponding STATUS bit is not updated and the INT line is not triggered if the masked event occurs. Any event happening while its corresponding interrupt is masked is lost. If an interrupt is masked after it has been triggered (event has occurred and has not yet been cleared), then the STATUS bit reflects the event until it is cleared and it does not trigger again if a new event occurs (because it is now masked).
Because some interrupts are sources of ON requests (see Table 6-6), source masking can be used to mask a specific device switch-on event. Because an active interrupt line INT is treated as an ON request, any interrupt not masked must be cleared to allow the execution of a SLEEP sequence of the device when requested.
The INT line polarity and interrupts clearing method can be configured using the INT_CTRL register.
An INT line event can be provided to the host in either SLEEP or ACTIVE mode, depending on the setting of the OSC_THERM_CTRL.INT_MASK_IN_SLEEP bit.
When a new interrupt occurs while the interrupt line INT is still active (not all interrupts have been cleared), then:
To clear the interrupt line, all status registers must be cleared. The clearing of all status registers is achieved by using a clear-on-read or a clear-on-write method. The clearing method is selectable though the INT_CTRL.INT_CLEAR bit. Once set, the clearing method applies to all bits for all interrupts.
INTERRUPT | ASSOCIATED EVENT | EDGES DETECTION | ON REQUEST | REG. GROUP | REG. BIT | DESCRIPTION |
---|---|---|---|---|---|---|
VSYS_MON | Internal event | Rising and falling | Never | INT1 | 6 | System voltage monitoring interrupt: Triggered when system voltage has crossed the configured threshold in VSYS_MON register. |
HOTDIE | Internal event | Rising and falling | Never | 5 | Hot-die temperature interrupt: The embedded thermal monitoring module has detected a die temperature above the hot-die detection threshold. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state. | |
PWRDOWN | PWRDOWN (terminal) | Rising and falling | Never | 4 | Power-down interrupt: Triggered when the event is detected on the PWRDOWN terminal. | |
RPWRON | RPWRON (terminal) | Falling | Always
(INT mask don't care) |
3 | Remote power-on interrupt: Triggered when a signal change is detected. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state. | |
LONG_PRESS_KEY | PWRON (terminal) | Falling | Never | 2 | Power-on long key-press interrupt. Triggered when PWRON is low during more than the long-press delay LONG_PRESS_KEY.LPK_TIME. | |
PWRON | PWRON (terminal) | Falling | Always
(INT mask don't care) |
1 | Power-on interrupt: Triggered when PWRON button is pressed (low) while the device is on. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state. | |
SHORT | Internal event | Rising | Yes
(if INT not masked) |
INT2 | 6 | Short interrupt: Triggered when at least one of the power resources (SMPS or LDO) has its output shorted. |
RESET_IN | RESET_IN (terminal) | Rising | Never | 4 | RESET_IN interrupt: Triggered when event is detected on RESET_IN terminal. | |
WDT | Internal event | Rising | Never | 2 | Watchdog time-out interrupt: Triggered when watchdog time-out has expired. | |
RTC_TIMER | Internal event | Rising | Yes
(if INT not masked) |
1 | Real-time clock timer interrupt: Triggered at programmed regular period of time (every second or minute). Running in ACTIVE, OFF, and SLEEP state, default inactive. | |
RTC_ALARM | Internal event | Rising | Yes
(if INT not masked) |
0 | Real-time clock alarm interrupt: Triggered at programmed determinate date and time. | |
VBUS | VBUS (terminal) | Rising and falling | Yes
(if INT not masked) |
INT3 | 7 | VBUS wake-up comparator interrupt. Active in OFF state. Triggered when VBUS present. |
GPADC_EOC_SW | Internal event | N/A | Yes
(if INT not masked) |
2 | GPADC software end of conversion interrupt: Triggered when conversion result is available. | |
GPADC_AUTO_1 | Internal event | N/A | Yes
(if INT not masked) |
1 | GPADC automatic periodic conversion 1: Triggered when result of conversion is either above or below (depending on configuration) reference threshold GPADC_AUTO_CONV1_LSB and GPADC_AUTO_CONV1_MSB. | |
GPADC_AUTO_0 | Internal event | N/A | Yes
(if INT not masked) |
0 | GPADC automatic periodic conversion 0: Triggered when result of conversion is either above or below (depending on configuration) reference threshold GPADC_AUTO_CONV0_LSB and GPADC_AUTO_CONV0_MSB. | |
GPIO_7 | GPIO_7 (terminal) | Rising and/or falling | Yes
(if INT not masked) |
INT4 | 7 | GPIO_7 rising- or falling-edge detection interrupt |
GPIO_6 | GPIO_6 (terminal) | Rising and/or falling | Yes
(if INT not masked) |
6 | GPIO_6 rising- or falling-edge detection interrupt | |
GPIO_5 | GPIO_5 (terminal) | Rising and/or falling | Yes
(if INT not masked) |
5 | GPIO_5 rising- or falling-edge detection interrupt | |
GPIO_4 | GPIO_4 (terminal) | Rising and/or falling | Yes
(if INT not masked) |
4 | GPIO_4 rising- or falling-edge detection interrupt | |
GPIO_3 | GPIO_3 (terminal) | Rising and/or falling | Yes
(if INT not masked) |
3 | GPIO_3 rising- or falling-edge detection interrupt | |
GPIO_2 | GPIO_2 (terminal) | Rising and/or falling | Yes
(if INT not masked) |
2 | GPIO_2 rising- or falling-edge detection interrupt | |
GPIO_1 | GPIO_1 (terminal) | Rising and/or falling | Yes
(if INT not masked) |
1 | GPIO_1 rising- or falling-edge detection interrupt | |
GPIO_0 | GPIO_0 (terminal) | Rising and/or falling | Yes
(if INT not masked) |
0 | GPIO_0 rising- or falling-edge detection interrupt |