SWCS095L August 2013 – February 2019 TPS659038-Q1 , TPS659039-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy of the 32-kHz clock output from the 16.384MHz crystal oscillator. To compensate for any inaccuracy, software must perform an external calibration of the oscillator frequency, calculate the drift compensation needed versus one time hour period, and load the compensation registers with the drift compensation value.
The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The process happens after the first second of each hour. The time between second 1 to second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: . It is therefore possible to adjust the compensation with a 1/32768-second time unit accuracy per hour and up to 1 second per hour.
Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2.
It is also possible to preload the internal 32-kHz counter with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers when setting the SET_32_COUNTER bit in the RTC_CTRL_REG register. This must be done when the RTC is stopped.
Figure 6-8 shows the RTC compensation scheduling.