SWCS049S June 2010 – August 2018 TPS65911
PRODUCTION DATA.
This section describes an example boot sequence. Each TPS65911x device supports a dedicated EEPROM boot sequence to match specific processor requirements. Fixed boot mode is the same in all TPS65911x devices. Boot mode selection is described in Section 6.5.2.
NOTE:
Figure 5-1 is for illustrative purposes only and does not describe any actual TPS65911x part number.PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tdsON1 | PWRHOLD rising edge to VIO | LDO5 enable delay | 66 × tCK32k = 2060 | µs | ||
tdsON2 | VIO to VDD2 enable delay | 64 × tCK32k = 2000 | µs | |||
tdsON3 | VDD2 to VDD1 enable delay | 64 × tCK32k = 2000 | µs | |||
tdsON4 | VDD1 to LDO4 enable delay | 64 × tCK32k = 2000 | µs | |||
tdsON5 | LDO4 to LDO3, LDO8 enable delay | 64 × tCK32k = 2000 | µs | |||
tdsON6 | LDO3 to LDO6 enable delay | 64 × tCK32k = 2000 | µs | |||
tdsON7 | LDO6 to CLK32KOUT rising-edge delay | 9 × 64 × tCK32k = 18000 | µs | |||
tdsON16 | CLK32KOUT to NRESPWON | NRESPWON2 rising-edge delay | 64 × tCK32k = 2000 | µs | ||
tdsONT | Total switch-on delay | 32 | ms | |||
tpd1 | PWRHOLD falling edge to NRESPWON | NRESPWON2 falling-edge delay | 2 × tCK32k = 62.5 | µs | ||
tpd1b | NRESPWON falling edge to CLK32KOUT low delay | 3 × tCK32k = 92 | µs | |||
tpd2 | PWRHOLD falling edge to supplies and reference disable delay | 5 × tCK32k = 154 | µs |