7.1 Overview

The TPS65912x device is an integrated power-management integrated circuit (PMIC), available in an 81- pin, 0.4-mm pitch, 3.6-mm × 3.6-mm DSBGA package. It is designed for applications including data cards, smart phones, wireless routers and switchers, LTE modems, industrial applications, GPS, and tablets. It provides four configurable step-down converter rails, with a power save mode for light loads. The TPS65912x device also provides ten external LDO rails - eight general purpose LDOs and two low-noise RF-LDOs. It also comes with two I2C interface channels or one SPI interface channel, 5 GPIOs, 32-kHz RC oscillator, and programmable power sequencer and control for supporting different processors and applications. The four step-down converter rails are consisting of four high frequency switch mode converters with integrated FETs. They are capable of synchronizing to an external clock input and supports switching frequency between 2.8 MHz and 3.5 MHz. The DCDC4 rail also includes a bypass switch that can be used to turn on and off high current loads. In addition, the DCDC rails support dynamic voltage scaling with a dedicated I2C interface. The eight general LDOs support 0.8 V to 3.3 V output, while the two low-noise LDOs support 1.6 V to 3.3 V. All LDOs and step-down converters can be controlled by the SPI or I2C interface. The power-up and power-down controller is configurable and programmable through OTP. The TPS65912x device includes a 32-kHz RC oscillator to sequence all resources during power up and power down. Configurable GPIOs with multiplexed feature are available on the TPS65912x device. The GPIOs can be configured and used as enable signals for external resources, which can be included into the power-up and power-down sequence. The general-purpose (GP) sigma-delta analog-to-digital converter (ADC) with two external input channels included in this device can be used as thermal or voltage and current monitors. Lastly, there is a long button-press detection that allows startup of the device with the hold of a button.

7.2 Functional Block Diagram

7.3 Linear Regulators

The power management core has 10 LDOs with various output voltage/current capabilities. Each LDO output voltage can be set independently through the communication bus (see LDO Voltage Settings table in Section 7.28.2) and the transition occurs immediately if the LDO is enabled.

7.4 Step-Down Converters

The synchronous step-down converter used in the power management core includes a unique hysteric PWM controller scheme which enables switch frequencies over 3 MHz, excellent transient and AC load regulation as well as operation with tiny and cost competitive external components.

The controller topology supports forced PWM Mode as well as Power Save Mode operation. Power Save Mode operation reduces the quiescent current consumption and ensures high conversion efficiency at light loads by skipping switch pulses.

A significant advantage of this architecture compared to other hysteretic PWM controller topologies is its excellent DC and AC load regulation capability in combination with low output voltage ripple over the entire load range which makes this part well suited for audio and RF applications.

Once the output voltage falls below the threshold of the error comparator a switch pulse is initiated and the high side switch is turned on. It remains turned on until a minimum on time of T_ONmin expires and the output voltage trips the threshold of the error comparator or the inductor current reaches the high side switch current limit. Once the high side switch turns off, the low side switch rectifier is turned on and the inductor current ramps down until the high side switch turns on again or the inductor current reaches zero.

7.4.7 Step-Down converter SOFT START

The step-down converters in TPS65912x have an internal soft-start circuit that controls the ramp up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within a time defined in Section 5. This limits the inrush current in the converter during start up and prevents possible input voltage drops when a battery or high impedance power source is used. The soft-start circuit is enabled after the start-up time t_Start has expired. For DCDC4, there is an option to set two different values for the start up and ramp time. For applications that require a fast response, set DCDC4_CTRL:RAMP_TIME = 1.

During soft start, the output voltage ramp up is controlled as shown in Figure 7-1.

Figure 7-1 Soft Start

The step-down converter enable/disable is part of the flexible power-up and power-down state machine. Each converter can be programmed such that it is powered up automatically in one of the 15 time slots after a power-on condition occurs or is controlled by a dedicated pin. Pins EN_1, EN_2, EN_3 and EN_4 as well as pins CLK_REQ1, CLK_REQ2 and PWR_REQ (SLEEP) can be mapped to any resource (LDOs, DC-DC converter, 32 kHz clock output or GPIO) to enable or disable it.

7.5 GPIOs

There are 5 GPIOs in TPS65912x. GPIO1 and GPIO2 are shared with the SPI interface, so they are not available if SPI is used. GPIO3, GPIO4 and GPIO5 are for general purpose use and are shared with the LED driver. GPIO1 and GPIO2 input and output stages are similar to GPIO3 however, they do not contain the LED current sink. If the output stage is programmed to push-pull, it pulls to the high-voltage set by VDDIO. With VDDIO being below the VDDIO undervoltage lockout, the high-side driver is disabled and the output is set to open drain.

Figure 7-2 GPIO Block for GPIO3, GPIO4, and GPIO5

7.6 Power State Machine

The embedded power controller (EPC) manages the state of the device and controls the power up sequence.

The EPC will support the following states:

The transitions for the state machine are shown figure below

7.7 Transition Conditions

• Device POWER ON enable conditions:
  • nPWRON signal low level
  • Or PWRHOLD signal high level
  • Or Pwr_hold_reg control bit set to 1 (default inactive)
  • Or interrupt flag active (default INT1 low) will generate a POWER ON enable condition during a fixed delay (During this delay it is expected processor to main acknowledge power by writing in Pwr_Hold reg or setting Power Hold pin to 1). Interrupt sources Generate wake up only if they are not Mask (OTP/Register dependant)
• Device POWER ON disable conditions:
  • nPWRON signal low level during more than the Long Press delay: PWON_LP_DELAY (can be disable though register programming). The interrupt corresponding to this condition is the PWRON_LP_IT in INT_STS_REG register.
  • Or Die temperature has reached the thermal shutdown threshold (THERM_TS=1)
  • Or DEV_OFF_RST control bit set to 1
• Device SLEEP enable condition:
  • SLEEP signal low level (Default, or high level depending of the programmed polarity)
  • AND DEV_SLP control bit set to 1
  • AND interrupt flag inactive (default INT1 high): no none masked interrupt pending
• Device has three different reset scenarios:
  • Full reset: all digital of device is reset
    • Caused by POR (Power On Reset) when VCCS < UVLO
  • General reset:
    • Caused by turn-off event with LOAD-OTP=1
    • Turn-off event by PWON_LP_OFF_RST bit set to 1
    • Optionally for TPS65912x1 by pin PWRON pulled low for longer than 100 ms

Figure 7-3 Embedded Power Control State Machine

Figure 7-4 STARTUP Flow for CONFIG2=1

Figure 7-4 is valid for CONFIG2=1. With CONFIG2=1, pins EN1, EN2, EN3 and EN4 are used as enable pins to enable one or several resources. Registers EN1_SET1 and EN1_SET2 define which converters or LDOs are controlled by pin EN1. Pins EN2, EN3, and EN4 are handled similarly.

Figure 7-5 STARTUP Flow for CONFIG2=0

Figure 7-5 is valid for CONFIG2=0. With CONFIG2=0, pins EN1, EN2, EN3 and EN4 are re-mapped to be DCDCx_SEL pins, defining which register is used to set the output voltage on a specific DC-DC converter. For example, DCDC1_SEL=0 sets the output voltage of DCDC1 to what is defined by register DCDC1_OP while DCDC1_SEL=1 sets the voltage defined by DCDC1_AVS. The DCDC2 voltage is defined by DCDC2_SEL and so forth.

LDO1 to LDO4 can be mapped to DCDCx_SEL pins. Register DEF_VOLT_MAPPING defines what LDO is controlled by what DCDCx_SEL pin.

In addition to this, CONFIG2=0 also re-maps pins SCL_AVS, SDA_AVS and SLEEP to be CLK_REQ1, CLK_REQ2 and PWR_REQ pins. The functionality is actually similar to the ENx pins.

Register EN1_SET1 and EN1_SET2 define what resource is controlled by PWR_REQ, EN2_SETx define the resource controlled by CLK_REQ1 and EN3_SETx defines the resources for CLK_REQ2.

Figure 7-6 SLEEP Flow

Figure 7-7 SHUTDOWN Flow for CONFIG2=1

Figure 7-8 SHUTDOWN Flow for CONFIG2=0

7.8 Implementation of Internal Power-Up and Power-Down Sequencing

The TPS65912x allows to internally enable resources during power up (going to ON state) and power down (going to OFF state) and for entering and exit of SLEEP mode. The internal power sequencing is defined in OTP memory programmed at TI. The sequencing allows to enable resources in 15 time slots during power-up and power-down. A resource can be associated to any of these 15 time slots that will be processed in the opposite direction during power down. There are 4 settings programmable for the delay, effective for all 15 time slots:

• TSLOT_LENGTH[1,0] = 00: 30 µs
• TSLOT_LENGTH[1,0] = 01: 200 µs
• TSLOT_LENGTH[1,0] = 10: 500 µs
• TSLOT_LENGTH[1,0] = 11: 2 ms

Resources may include:

• Step-down converters
• LDOs
• 32-kHz clock outputs
• nRESPWRON output

Resources that are not part of the automatic sequencing may be configured such that they are enabled by external pins or by their enable Bit in the register set. Resources that are enabled automatically should not be assigned to an external enable pin. A "break point" can be defined that stops power-up sequencing and continues upon the status of the voltage monitor. This allows to hold power-up until the voltage of the voltage monitors exceeds a certain limit.

As shown in Figure 7-9, resources can be mapped to any of the time slots with none, one or multiple resources for any time slot.

For SLEEP entry and SLEEP exit, only three time slots are used with a 120-µs delay between time slots.

Figure 7-9 Internal Power-Up Example

7.9 EN1, EN2, EN3, EN4, Resources Control

ENx control signal can turn ON/OFF Resources based on register setting. It is possible to assigned several resources to one ENx control signal. It is possible to assigned resource to several ENx (active control will be dominant). ENx configuration is done by OTP; however, it is possible to change this setting after power up inside ENx_SETx registers. ENx is effective only in Active or SLEEP mode. See for further details at Section 7.11 on how the pin status on ENx is interpreted.

Figure 7-10 ENx Architecture

7.10 SLEEP State Control

The sleep control input on pin SLEEP is used to move the IC into Sleep state where resource behavior (DC-DC, LDOs, 32-kHz clock output, and thermal monitor) are defined in registers called SET_OFF, KEEP_ON and DEF_VOLT.

7.11 Registers SET_OFF, KEEP_ON and DEF_VOLT Used in SLEEP State; CONFIG2 = 1

Registers SET_OFF; KEEP_ON and DEF_VOLT are used to define the behavior of a resource in SLEEP state. SLEEP state is entered based on the signal at pin SLEEP if enabled by bit DEVCTRL2:SLEEP_ENABLE. The polarity of an active sleep signal can be changed using bit DEVCTRL2:SLEEP_POL.

DCDC1 to DCDC4 and LDO1 to LDO4 allow to change the output voltage depending on ACTIVE state vs SLEEP state. See the following for programming of SET_OFF, KEEP_ON and DEF_VOLT:

• Keep resource enabled in SLEEP state: SET_OFF=x , KEEP_ON=1
• Turn resource off in SLEEP state: SET_OFF=1 , KEEP_ON=0
• Set resource to ECO mode in SLEEP state: SET_OFF=0, KEEP_ON=0
• Change the output voltage of a resource when in SLEEP state:
  • DEF_VOLT=0: voltage defined by _OP register
  • DEF_VOLT=1: voltage defined by _AVS register

7.12 Registers SET_OFF, KEEP_ON and DEF_VOLT Used for Resources Assigned to an External Enable Pin; CONFIG2 = 1

As described in Section 7.8, a resource can be assigned to an enable pin. In this case SLEEP state has no effect on such a resource but its behavior is defined by the state of the enable pin. Registers SET_OFF, KEEP_ON and DEF_VOLT are re-mapped and used to define how a resource is acting when the enable pin is set low or is set high. The definition for an high signal on ENx is similar to an ACTIVE state while a low signal on ENx equals the behavior in SLEEP state. See the following for a detailed description:

• Enable resource when ENx pin is set high: SET_OFF=x , KEEP_ON=x
• Disable resource when ENx pin is set low: SET_OFF=1 , KEEP_ON=0
• Set resource to ECO when ENx pin is set low: SET_OFF=0, KEEP_ON=0
• Change the output voltage of a resource when pin ENx is set low:
  • DEF_VOLT=0: voltage defined by _OP register
  • DEF_VOLT=1: voltage defined by _AVS register

7.13 Registers SET_OFF, KEEP_ON and DEF_VOLT for Resources Assigned to Pins PWR_REQ, CLK_REQ1 and CLK_REQ2; CONFIG2 = 0

With the CONFIG2 pin tied to GND, pins ENx are used as voltage select pins DCDCx_SEL for the DC-DC converters and for LDOs assigned to these pins by register DEF_VOLT_MAPPING. There pins are only used to switch the output voltage between two values as defined in registers _OP and _AVS.

• DCDCx_SEL=0: _OP registers are used to define the output voltage
• DCDCx_SEL=1: _AVS registers are used to define the output voltage

The basic function of enabling or disabling resources is re-mapped to pins PWR_REQ, CLK_REQ1 and CLK_REQ2. The pin function is managed by registers ENx_SETx in the following list. Register EN4_SETx is not used and should be set 0x00.

• PWR_REQ: EN1_SETx
• CLK_REQ1: EN2_SETx
• CLK_REQ2: EN3_SETx

7.14 Voltage Scaling Interface Control Using _OP and _AVS Registers with I²C or SPI Interface

A dedicated I²C_AVS interface is available for voltage scaling functionality. It works in three different modes.

• I²C voltage scaling interface where voltage target can be setup in DCDCx_OP registers.
• AVSx pin called DCDCx_SEL can be used as roof or floor configuration where the DC-DC voltage switches between the value defined in the DCDCx_OP register and the DCDCx_AVS register.

The slew rate of VDDX voltage supply reaching a new programmed value is programmable though the VDDx_REG register.

Both I²C interfaces are compliant with HS-I²C specification (100 kbits/s, 400 kbits/s, or 3.4 Mbits/s)

CONFIG1=0: OTP option A is selected

CONFIG1=1: OTP option B is selected

Figure 7-11 DC-DC Voltage Scaling Architecture

7.15 Voltage Scaling Using the VCON Decoder on Pins VCON_PWM and VCON_CLK

Output voltage control for DCDC1 defaults to internal registers DCDC1_OP and DCDC1_AVS or DCDC_SEL pins for CONFIG2=0. With DCDC1_CTRL:VCON_ENABLE = 1, voltage scaling is set to VCON.

When enabled, VCON decodes the VCON_PWM from VCON_CLK. It validates the generated output voltage does not exceed 1.1 V when 25-mV step size is selected. For PWM ratios 0/32 to 7/32, the output voltage will clip to 1.1 V. Four ranges can be selected by setting the VCON_RANGE[1:0] bits in register DCDC1_CTRL. The range bits towards the converters will be adjusted according to the VCON_RANGE bits.

The VCON_CLK and VCON_PWM signal need to be active and one complete frame received by TPS65912x before it is enabled with DCDC1_CTRL:VCON_ENABLE. Once DCDC1_CTRL:VCON_ENABLE is set to 0, the voltage setting is reverted back to register DCDC1_AVS or DCDC1_OP depending on the DCDC1_SEL pin. The range bits are fed through as set in the DCDC1_LIMIT register. For VCON mode, no DVS, MAX voltage comparison nor RANGE information is checked within the VCON DECODER block (but in the digital core as described in the data sheet).

For TPS659121(A) only: VCON is automatically disabled by internally clearing DCDC1_CTRL:VCON_ENABLE once the PWR_REQ pin goes LOW. It not automatically turn on but will have to be enabled in software again after PWR_REQ was set HIGH.

The function calculates the desired converter voltage based on the in incoming PWM information. The max CLK frequency is 30 MHz. The period of the PWM signal is 1/32 of VCON_CLK. The decoding follows Equation 1.

Figure 7-12 VCON Voltage Scaling Architecture

7.16 Configuration Pins CONFIG1, CONFIG2 and DEF_SPI_I2C-GPIO

The TPS65912x contains two banks of OTP memory that define the default settings programmed. CONFIG1 selects between these two banks of memory. The logic level at pin CONFIG1 in state CONFIG determines which of the OTP banks is used and its content is copied to the user registers to set all OTP configurable options like default voltages and power-up timing.

CONFIG2 is used to remap functions to pins. For CONFIG2=1, pins EN1 to EN4 as well as SCL_AVS, SDA_AVS and SLEEP are active. With CONFIG2=0, these pins are used as DCDCx_SEL and CLK_REQ1, CLK_REQ2 and PWR_REQ pins.

DEF_SPI_I2C-GPIO defines whether the SPI interface or the I²C interface is used as the standard communication interface. DEF_SPI_I2C-GPIO =0 defines SPI as the standard interface associated to pins SCL_SCK, SDA_MOSI, GPIO1_MISO and GPIO2_CE. CONFIG1, CONFIG2 and DEF_SPI_I2C-GPIO should be tied to GND for a low level and to LDOAO for a logic high level.

Pins CONFIG1, CONFIG2 and DEF_SPI_I2C-GPIO should not be switched in operation but hardwired to a logic low level (GND) or a logic high level by connecting them to the LDOAO voltage.

7.17 VDDIO Voltage for Push-Pull Output Stages

There is a number of outputs that can either be configured as a push-pull output or are push-pull outputs only. Any pin with a push-pull output stage will generate its output high level by the voltage applied to pin VDDIO. The input voltage range on VDDIO is 1.6 V to 3.3 V with an undervoltage lockout below 1.6 V. With a VDDIO voltage below the undervoltage lockout threshold, the high side driver of the push-pull output stages are disabled and the output default back to open drain. Pins affected are listed below:

• nRESPWRON push-pull or open drain defined by DEVCTRL:Bit3
• INT1 push-pull or open drain defined by DEVCTRL2:Bit6
• VSUP_OUT same pin with nRESPWRON, definition by DEVCTRL:Bit3
• GPIO1, GPIO2: push-pull only
• GPIO3, GPIO4, GPIO5: push-pull or open drain managed by GPIOx registers
• 32-kHz CLKOUT: alternative function to OMAP_WDI (input); switched to output by CONFIG2=0, switched to input with CONFIG2=1; push-pull only if output with CONFIG2=0: CPCAP_WDI is set to 0 with CONFIG2=1: CPCAP_WDI is the output of the AND gate

7.18 Digital Signal Summary

• SLEEP:
  • When all SLEEP condition are met (no pending interrupt, Sleep Ball low, Sleep register set to 1), The IC is transitioning to SLEEP which impact LDO/DC-DC behavior based on settings defined in registers SET_OFF, KEEP_ON and DEF_VOLT. An interrupt or a SLEEP pin level change will cause a transition back to ACTIVE state. This input signal is level sensitive and no debouncing is applied. SLEEP is configurable and is disabled by default, so at power up its status will be ignored. In a user register it can be enabled and its active level changed between active HIGH or active LOW using bits SLEEP_POL and SLEEP_ENABLE in register DEVCTRL2.
• PWRHOLD:
  • PWRHOLD pin can be used as ON/OFF signal input (when nPWRON and Interrupt not used). It can also be used as acknowledge (Maintain Power) of power-up sequence trigger by interrupt or press of nPWRON. This input signal is level sensitive and no debouncing is applied. Rising and/or falling edge of PWRHOLD is highlighted through an associated interrupt if interrupt is unmasked.
• NRESPWRON/VSUP_OUT:
  • NRESPWRON signal is used as the reset to the processor and is in VDDIO domain. It is held low until the ACTIVE state is reached. See Section 7.19, Section 7.20 to get detailed timing.
  • VSUP_OUT is the output of the voltage monitor that can alternatively be used as a reset to a processor or included in the power-up sequencing such that it hold power up until its output is HIGH or the device power down when LOW.
• 32KCLKOUT:
  • This signal is the output of the 32K RC oscillator, which can be enabled or not during the power-on sequence. It can be enabled and disabled by register bit, during ACTIVE state of the device.
• nPWRON:
  • The nPWRON input is connected to an external button. A debounced falling edge on this signal causes a OFF to ACTIVE state transition of the device. If the device is in ACTIVE/SLEEP mode then a low level on this signal generates an interrupt. If the nPWRON signal is low for more than the PWON_TO_OFF_DELAY delay and the corresponding interrupt is not acknowledged by the external processor in TBDs then the device will go to OFF state.
• INT1:
  • INT1 signal (active low) warns the host processor of any event that occurred on the TPS65912x device. The host processor can then poll the interrupt from the interrupt status register via I²C to identify the interrupt source. A low level indicates an active interrupt, highlighted in the INT_STSx registers. Interrupt flag active will generate a POWER ON enable condition pulse of length TDOINT1 only when the device is in OFF state (when NRESPWRON signal is low). The POWER ON enable condition pulse will occur only if the interrupt status bit is initially low (no previous interrupt pending in the status register). Interrupt status register must be cleared first to allow device POWER OFF during the TDOINT1 pulse duration. Any of the interrupt sources can be masked programming INT_MSKx registers. The default setting is masking all interrupts. When an interrupt is masked, its corresponding interrupt status bit is still updated, but the INT1 flag is not activated. Interrupt source masking can be used to mask a device switch-on event. The INT output can be programmed as push-pull or open drain output stage with either active LOW or active HIGH output defined by two OTP settings.
• GPIO1, GPIO2, GPIO3, GPIO4, GPIO5:
  • GPIO functionality are muxed with LED and SPI interface. It can be used for event detection or control of external resources during power up.
• VCCS_VIN_MON:
  • This is the input for the internal undervoltage lockout monitor. The block provides a selectable low battery warning as well as a undervoltage shutdown.
• VCON_CLK; VCON_PWM:
  • Clock and data input for voltage scaling of DCDC1. The feature is enabled by TBD Bit. When enabled, voltage scaling through DCDC1_OP and DCDC1_AVS registers is blocked.
• CLK, MOSI, MISO,CE:
  • Clock chip enable and master in slave out (MISO) and master out slave in MOSI pins for the SPI interface. The pins are shared with the standard I²C interface SCL and SDA and GPIO1 and GPIO2
• DEF_SPI_I2C-GPIO:
  • Defines whether multifunction pins are used for the SPI interface or for the I²C interface and GPIOs. For DEF_SPI_I2C-GPIO = 0, the function is assigned to the SPI interface on pins CLK, MOSI, MISO, CE. For DEF_SPI_I2C-GPIO = 1, the function is assigned to the I²C interface and GPIOs on pins SCL, SDA, GPIO1 and GPIO2.
• SCL_AVS, SDA_AVS:
  • Power I²C interface, typically used for DVS on the step-down converters. There is a Bit on each step-down converter to switch the voltage scaling registers from the standard I²C interface or SPI interface to the power-I²C interface. When switched to power-I²C, the register is blocked for access through the standard interface.

7.19 TPS659121 On/Off Operation With E450, E500

7.19.1 TPS659121 Power Up From Battery or 5-V USB Supply; CONFIG1=LOW

PWRHOLD is tied to the supply voltage so TPS65912x starts its power-up sequencing once the input voltage is above the UVLO threshold. After DCDC2, DCDC3 and LDO10 are powered, further power up is pending the status of the voltage monitor based on the VIN_MON voltage. Once the voltage is above the threshold, VSUP_OUT goes high and power-up sequencing continues. DCDC1 and LDO1 are controlled by the status of their enable pin PWR_REQ. CLK_REQ1 and CLK_REQ2 are logically OR´d to enable LDO4 and LDO5.

Figure 7-13 TPS659121 Battery or 5 V-USB Power-Up With CONFIG1=LOW

7.19.2 TPS659121 Power Up From 3.3-V Host Supply; CONFIG1=LOW

PWRHOLD and VIN_MON are directly tied to the supply input of 3.3 V. TPS65912x will power up DCDC2 and LDO10 first and wait for VSUP_OUT going high to continue with LDO2, LDO3, LDO8, and LDO9. PWR_REQ and CLK_REQ pins are used to directly control DCDC1 and LDO1 or LDO4 and LDO5, respectively similar to the 5-V USB power up.

Figure 7-14 TPS659121 3.3-V Host Power Up With CONFIG1=LOW

7.20 TPS659122 On/Off Operation for CONFIG1=HIGH

TPS659122 with CONFIG1=HIGH addresses a chip set with a start-up sequencing as defined in the following. See the default voltage table given under , Figure 7-15, Figure 7-16, and Figure 7-17.

7.20.1 TPS659122 Power Up With CONFIG1=HIGH

PWRHOLD is tied to the supply voltage, so TPS659122 starts its power-up sequencing once the input voltage is above the UVLO threshold. After the DC-DC converters and LDOs have started, the nRESPWRON signal is released and TPS659122 is ready to respond to commands over its digital interfaces. Pin CLK_REQ1 is used to enable / disable LDO1 while CLK_REQ2 controls the enable function for LDO3. DCDC4 is enabled during the automatic power-up sequence along with DCDC2. After nRESPWRON is released high, enable control for DCDC4 is given to pin SLEEP, so pulling the SLEEP pin low will disable DCDC4 after the power-up cycle is completed and nRespwron has been released.

Figure 7-15 TPS659122 Power Up With CONFIG1=HIGH

7.20.2 TPS659121, TPS659122 Power-Off Sequence With CONFIG1=HIGH

Once the voltage at the input to the voltage monitor on pin VI_MON drops below the threshold, an interrupt at pin INT1 is generated by pulling INT1=LOW. After a programmable delay of VMON_DELAY[1,0] of up to 250 µs, VSUP_OUT goes LOW which triggers the shutdown cycle after another 2-ms delay. During shutdown, all converters and LDOs are disabled at the same time.

Figure 7-16 TPS659121, TPS659122 Power Cut With CONFIG1=HIGH

7.21 TPS659122 On/Off Operation for CONFIG1=LOW

TPS659122 with CONFIG1=LOW addresses a different chipset and, therefore, has default voltage settings and start-up sequencing defined differently compared to CONFIG1=HIGH. See the default voltage table given under and Figure 7-17.

7.21.1 TPS659122 Power Up With CONFIG1=LOW

PWRHOLD is tied to the supply voltage, so TPS659122 starts its power-up sequencing once the input voltage is above the UVLO threshold. After the DC-DC converters and LDOs have started, the nRESPWRON signal is released and TPS659122 is ready to respond to commands over its digital interfaces.

Figure 7-17 TPS659122 Power Up With CONFIG1=LOW

7.22 Interfaces

There are three interfaces in the TPS65912x device. A high-speed I²C interface that has access to all register, a SPI interface that can optionally be used to access all registers and a high-speed power I²C interface that can be used to dynamically change the output voltage of the DC-DC converters. The power I²C interface only has access to the voltage scaling registers of the DC-DC converters. If it is activated by a selection bit, the registers it is using are blocked for the general-purpose I²C or SPI interface. All interfaces are active in ACTIVE state only; in all other states, the interfaces are held in a reset and cannot be used to access TPS65912x.

7.23 Serial Peripheral Interface

The serial peripheral interface (SPI ) uses 4 signals: A chip enable SPI_CE, the clock from the bus master SPI_CLK, an input port SPI_MOSI (Master In Slave Out), and an output port SPI_MISO (Master Out Slave In). The read/write Bit is followed by a 8-bit register address followed by 7 bits of unused bits followed by the data bits. The MISO output is set to high impedance when TPS65912x is not addressed by setting CE = LOW; thus allowing multiple slaves on the SPI bus.

Figure 7-18 SPI READ and WRITE Protocol

Figure 7-19 SPI BURST READ and BURST WRITE Protocol

7.24 I²C Interface

I²C is a 2-wire serial interface developed by NXP® (formerly Philips Semiconductor) (see I²C-Bus Specification and user manual). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The TPS65912x works as a slave and supports the following data transfer modes, as defined in the I²C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write mode). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents are loaded when voltage is applied to TPS65912x higher than the undervoltage lockout level (UVLO) of 2.4 V. Once the device is in ACTIVE state and is turned off, Bit LOAD-OTP [DEVCONTROL:Bit6] forces a reload of the registers when LOAD-OTP = 1 (default). With LOAD-OTP = 0, register content is not changed unless the supply voltage drops below the UVLO threshold. The I²C interface is running from an internal oscillator that is automatically enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S mode, and it is referred to as HS mode. The TPS65912x supports 7-bit addressing; 10-bit addressing and general call address are not supported.

7.24.3 H/S-Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions are used to secure the bus in HS mode.

Attempting to read data from register addresses not listed in this section results in a readout of FFh.

Figure 7-20 START and STOP Conditions

Figure 7-21 Bit Transfer on the Serial Interface

Figure 7-22 Acknowledge on the I²C Bus

Figure 7-23 Bus Protocol

Figure 7-24 I²C Interface WRITE to TPS65912x; F/S mode

Figure 7-25 I²C Interface READ from TPS65912x; F/S mode

7.25 Thermal Monitoring and Shutdown

Two thermal-protection modules monitor the junction temperature of the device versus two thresholds:

• Hot-Die temperature threshold
• Thermal Shutdown temperature thresholds

When the Hot-Die temperature threshold is reached, an interrupt is sent to SW to close the non-critical running tasks.

The output of both thermal protection modules is logically OR’d. When the Thermal Shutdown temperature threshold is reached the TPS65912x device is set under reset and a transition to OFF state is initiated. Then the POWER ON enable conditions of the device will not be taken into consideration until the die temperature has decreased below the Hot-Die threshold. An hysteresis is applied to the Hot-Die and shutdown threshold, when detecting a falling edge of temperature, and both detection are debounced in order to avoid any parasitic detection. The TPS65912x device allows to program four hot-die temperature thresholds in order to increase the flexibility of the system.

By default, the thermal protection is enabled in ACTIVE state, but It can be disabled through programming the THERM_REG register. The thermal protection is automatically enabled during an OFF to ACTIVE state transition and will be kept enabled in OFF state after a switch-off sequence caused by a thermal shutdown event. Transition to OFF-state sequence caused by a thermal shutdown event will be highlighted in the INT_STS_REG status register. Recovery from this OFF state is initiated (switch-on sequence) when the die temperature falls below the Hot-Die temperature threshold.

Hot-Die and thermal shutdown temperature threshold detections state can be monitored or masked by reading or programming the THERM_REG register. Hot-Die interrupt can be masked by programming the INT_MSK_REG register.

7.26 Load Switch

The load switch on TPS65912x can be used as the following:

• Bypass switch for DCDC4
• Current limited switch if TPS65912x is used in USB powered applications
• A switch to turn on and off high current loads like SD cards

Figure 7-26 Load Switch Connected as USB Input Current Limited Switch

Figure 7-27 Load Switch Connected as BYPASS Switch for DCDC4

There is a register called LOADSWITCH associated to the load switch function allowing it to be used as a bypass switch on DCDC4 or as a current limited switch. There are 4 programmable current limits between 90 mA (typically) and 2.5 A with the default current defined by an OTP setting. The enable bits are mapped to external pins called EN_LS0 and EN_LS1. The status of the pins will be copied to the register in state CONFIG, so the usage of the load switch can be externally predefined. In ACTIVE state (or SLEEP), the functionality of the load switch is controlled by the ENABLE0 and ENABLE1 bits only to turn the load switch ON, turn it off or assign it to a comparator as a bypass switch for DCDC4. When the enable function is set to the comparator, it is auto-enabled based on the voltage differential V_in to V_out on the step-down converter, DCDC4.

In case the load switch is used as a bypass switch for DCDC4, there are two additional features. The following features are enabled with LOADSWITCH:ENBALE[1,0] = 10 or 11:

• Forced PWM mode of DCDC4 is blocked if the bypass switch is closed
• The bypass switch is opened automatically when there is a overvoltage condition; LOADSWITCH:ENBALE[1,0] is automatically set "00" in an over-voltage event so the switch is opened

In applications where the load switch is used as an USB input current limited switch or as a load switch on the output of a DC-DC converter to LDO, the above features must be disabled. This is the case when the load switch is enabled with LOADSWITCH:ENBALE[1,0] = 01.

See the LOADSWITCH register in Section 7.28.2 for further details.

Figure 7-28 Load Switch Timing for LOADSWITCH:ENABLE[1,0] = 10 or 11

7.27 LED Driver

GPIO3, GPIO4, and GPIO5 can alternatively be configured to drive LEDs by setting Bit GPIO_SEL = 1 in register GPIOx. This will switch the output stage to a current sink controlled by the LED control registers LEDx_CTRLx, LED_RAMP_UP_TIME, LED_RAMP_DOWN_TIME and LED_SEQ_EN. LEDs are enabled in the LED_SEQ_EN register. The LED current sink is PWMd with the duty cycle defined LEDx_CTRL7:LEDx_PWM[4,0]. All 3 GPIOs should either be assigned as a LED driver or as a standard GPIO.

To turn on LEDA with a constant current of 10 mA:

• Set the GPIO as a LED current sink output: GPIOA:GPIO_SEL = 1
• Set the constant current to 10 mA: LEDA_CTRL1:LEDA_CURRENT[3,0] = 0b0100
• Set the PWM duty cycle to 100%: LEDA_CTRL7:LEDA_PWM[4,0] = 0b11111
• Enable the LEDA current sink: LED_SEQ_EN:LEDA_EN = 1

In addition to just turn on and turn off an LED, the LED driver allows to set LED sequence to perform a flash sequence in hardware by enabling the flash sequencer by Bit LEDx_SEQ_EN for each of the three LEDs.

Figure 7-29 LED Sequencer

The LED driver allows to set a dc current in the range from 2 mA to 20 mA for each LED. In addition to this, there is a LED flash sequence programmable defined by T1, T2, T3, T4, and TP. Within these time slots the LED can be turned on defined by LEDx_ON_TIME with a defined ramp-up slope set with register LED_RAMP_UP and ramp-down slope. The slopes are set to the same value for all three LEDs but other parameters are programmable independently. Figure 7-29 shows an LED flash cycle. The ramp enable bits define whether the current immediately steps to its defined value (LEDx_CURRENT[3,0]) or ramps with a certain slope.

• During a sequence if LEDx_RAMP_EN=0, current immediately goes to LEDx_I[3:0]
• During a sequence if LEDx_RAMP_EN=1, current steps up and down to LEDx_I[3:0] with a certain slope

In addition, the LED current is pulse-width modulated with a duty cycle defined in register LEDx_CTRL7.

For the LED driver to operate properly, the time for RAMP-UP + LED_ON + RAMP_DOWN must be smaller than the sequence Tn (with n = 1, 2, 3, 4, P).

7.28 Memory