SLVSDC2C February 2016 – August 2021 TPS65981
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The TPS65981 is capable of controlling an external high-voltage, common-drain back-to-back NMOS FET switch path to source or sink power up to the maximum limit of the USB PD specification: 20 V at 5 A of current. The TPS65981 provides external control and sense to external NMOS power switches for currents greater than 3 A. This path is bi-directional for either sourcing current to VBUS or sinking current from VBUS. The external NMOS switches are back-to-back to protect the system from large voltage differential across the FETs as well as blocking reverse current flow. Each NFET has a separate gate control. HV_GATE2 is always connected to the VBUS side and HV_GATE1 is always connected to the opposite side, referred to as PP_EXT. Two sense pins, SENSEP and SENSEN, are used to implement reverse current blocking, over-current protection, and current sensing. The external path may be used in conjunction with the internal path. For example, the internal path may be used to source current from PP_HV to VBUS when the TPS65981 is acting as a power source and the external path may be used to sink current from VBUS to PP_EXT to charge a battery when the TPS65981 is acting as a sink. The internal and external paths must never be used in parallel to source current at the same time or sink current at the same time. The current limiting function will not function properly in this case and may become unstable.