SLVSDC2C February 2016 – August 2021 TPS65981
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Once the components are routed, the rest of the area can be used to route all of the additional I/O. After all nets have been routed place polygonal pours around the PP_5V0, PP_HV, and VBUS pins of the TPS65981 GND pins to the GND vias. Refer to Figure 12-12 for the final top routing.