SLVSFN7 September   2020 TPS65982DMC

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Adapter Power Switch Characteristics
    8. 6.8  USB Endpoint Requirements and Characteristics
    9. 6.9  Analog-to-Digital Converter (ADC) Characteristics
    10. 6.10 Input/Output (I/O) Requirements and Characteristics
    11. 6.11 I2C Slave Requirements and Characteristics
    12. 6.12 SPI Master Characteristics
    13. 6.13 Single-Wire Debugger (SWD) Timing Requirements
    14. 6.14 ADP_POWER_CFG Configuration Requirements
    15. 6.15 Thermal Shutdown Characteristics
    16. 6.16 Oscillator Requirements and Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adapter Power Switch
        1. 8.3.1.1 Adapter Switch with RSENSE
        2. 8.3.1.2 Adapter Switch without RSENSE
        3. 8.3.1.3 External Current Sense
        4. 8.3.1.4 External Current Limit
        5. 8.3.1.5 Soft Start
        6. 8.3.1.6 ADP_POWER_CFG
      2. 8.3.2  USB Type-C Port Data Multiplexer
        1. 8.3.2.1 USB2.0 Low-Speed Endpoint
      3. 8.3.3  Power Management
        1. 8.3.3.1 Power-On and Supervisory Functions
        2. 8.3.3.2 Supply Switch-Over
        3. 8.3.3.3 RESETZ and MRESET
      4. 8.3.4  Digital Core
      5. 8.3.5  System Glue Logic
      6. 8.3.6  Power Reset Congrol Module (PRCM)
      7. 8.3.7  Interrupt Monitor
      8. 8.3.8  ADC Sense
      9. 8.3.9  I2C Slave
      10. 8.3.10 SPI Master
      11. 8.3.11 Single-Wire Debugger Interface
      12. 8.3.12 ADC
        1. 8.3.12.1 ADC Divider Ratios
        2. 8.3.12.2 ADC Operating Modes
        3. 8.3.12.3 Single Channel Readout
        4. 8.3.12.4 Round Robin Automatic Readout
        5. 8.3.12.5 One Time Automatic Readout
      13. 8.3.13 I/O Buffers
        1. 8.3.13.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 8.3.13.2 IOBUF_OD
        3. 8.3.13.3 IOBUF_I2C
        4. 8.3.13.4 IOBUF_GPIOHSPI
        5. 8.3.13.5 IOBUF_GPIOHSSWD
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Application Code
      5. 8.4.5 Flash Memory Read
      6. 8.4.6 Invalid Flash Memory
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. 8.5.2.1 I2C Interface Description
        2. 8.5.2.2 I2C Clock Stretching
        3. 8.5.2.3 I2C Address Setting
        4. 8.5.2.4 Unique Address Interface
        5. 8.5.2.5 I2C Pin Address Setting
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB4 Device Application with Host Charging
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Power Supply Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 USB Power Delivery Source Capabilities
          2. 9.2.1.2.2 USB Power Delivery Sink Capabilities
          3. 9.2.1.2.3 Supported Data Modes
          4. 9.2.1.2.4 USB4 Hub Controller & PD Controller I2C Communication
          5. 9.2.1.2.5 Dock Management Controller & PD Controller I2C Communication
          6. 9.2.1.2.6 SPI Flash Options
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 1VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 ADP_IN 3.3 V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement
      2. 11.2.2 Recommended Via Size and Trace Widths
      3. 11.2.3 Adapter Input Power Routing
      4. 11.2.4 USB2 Routing
      5. 11.2.5 Oval Pad for BGA Fan Out
      6. 11.2.6 Top and Bottom Layer Complete Routing
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.13.5 IOBUF_GPIOHSSWD

Figure 8-15 shows the I/O buffers for the SWD interface. The CLK input path is a comparator with a pullup SWD_RPU on the pin. The data I/O consists of an identical input structure as the CLK input but with a tri-state CMOS output driver.

GUID-4915341A-6311-4AD8-91AB-0A79E6EE521A-low.gifFigure 8-15 IOBUF_GPIOHSSWD