SLVSFN7 Data sheet

SLVSFN7 September 2020 TPS65982DMC

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

ZBH|96
- MPBGAL7A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.10 Input/Output (I/O) Requirements and Characteristics

Recommended operating conditions; T_A = –10 to +85°C unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SPI
SPI_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
SPI_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
SPI_HYS	Input hysteresis voltage	LDO_3V3 = 3.3 V	0.2			V
SPI_ILKG	Leakage current	Output is Hi-Z, V_IN = 0 to LDO_3V3	–1		1	μA
SPI_VOH	SPI output high voltage	I_O = –8 mA, LDO_3V3 = 3.3 V	2.9			V
SPI_VOH	SPI output high voltage	I_O = –15 mA, LDO_3V3 = 3.3 V	2.5			V
SPI_VOL	SPI output low voltage	I_O = 10 mA			0.4	V
SPI_VOL	SPI output low voltage	I_O = 20 mA			0.8	V
SWDIO
SWDIO_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
SWDIO_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
SWDIO_HYS	Input Hysteresis Voltage	LDO_3V3 = 3.3 V	0.2			V
SWDIO_ILKG	Leakage current	Output is Hi-Z, V_IN = 0 to LDO_3V3	–1		1	μA
SWDIO_VOH	Output high voltage	I_O = –8 mA, LDO_3V3 = 3.3 V	2.9			V
SWDIO_VOH	Output high voltage	I_O = –15 mA, LDO_3V3 = 3.3 V	2.5			V
SWDIO_VOL	Output low voltage	I_O = 10 mA			0.4	V
SWDIO_VOL	Output low voltage	I_O = 20 mA			0.8
SWDIO_RPU	Pullup resistance		2.8	4	5.2	kΩ
SWDIO_TOS	SWDIO output skew to falling edge SWDCLK		–5		5	ns
SWDIO_TIS	Input setup time required between SWDIO and rising edge of SWCLK		6			ns
SWDIO_TIH	Input hold time required between SWDIO and rising edge of SWCLK		1			ns
SWDCLK
SWDCL_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
SWDCL_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
SWDCL_THI	SWDIOCLK HIGH period		0.05		500	μs
SWDCL_TLO	SWDIOCLK LOW period		0.05		500	μs
SWDCL_HYS	Input hysteresis voltage	LDO_3V3 = 3.3 V	0.2			V
SWDCL_RPU	Pullup resistance		2.8	4	5.2	kΩ
GPIO, MRESET, RESETZ, ADP_POWER_CFG
GPIO_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
GPIO_VIH	High-level input voltage	VDDIO = 1.8 V	1.25			V
GPIO_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
GPIO_VIL	Low-level input voltage	VDDIO = 1.8 V			0.63	V
GPIO_HYS	Input hysteresis Voltage	LDO_3V3 = 3.3 V	0.2			V
GPIO_HYS	Input hysteresis Voltage	VDDIO = 1.8 V	0.09			V
GPIO_ILKG	I/O leakage current	INPUT = 0 V to VDD	–1		1	μA
GPIO_RPU	Pullup resistance	Pullup enabled	50	100	150	kΩ
GPIO_RPD	Pulldown resistance	Pulldown enabled	50	100	150	kΩ
GPIO_DG	Digital input path deglitch			20		ns
GPIO_VOH	GPIO output high voltage	I_O = –2 mA, LDO_3V3 = 3.3 V	2.9			V
GPIO_VOH	GPIO output high voltage	I_O = –2 mA, VDDIO = 1.8 V	1.35			V
GPIO_VOL	GPIO output low voltage	I_O = 2 mA, LDO_3V3 = 3.3 V			0.4	V
GPIO_VOL	GPIO output low voltage	I_O = 2 mA, VDDIO = 1.8 V			0.45	V
HRESET
HRESET_VIH	High-level input voltage		1.25			V
HRESET_VIL	Low-level input voltage				0.63	V
HRESET_HYS	Input hysteresis Voltage		.09			V
HRESET_ILKG	I/O leakage current	INPUT = 0 V to LDO_1V8D	–1		1	μA
HRESET_THIGH	HRESET minimum high time to assert a reset condition.		2.0			ms
HRESET_TLOW	HRESET minimum low time to deassert a reset condition.		2.0			ms
I2C_IRQ1Z, I2C_IRQ2Z
OD_VOL	Low level output voltage	I_OL = 2 mA			0.4	V
OD_LKG	Leakage current	Output is Hi-Z, V_IN = 0 to LDO_3V3	–1		1	μA