SLVSFN7 September   2020 TPS65982DMC

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Adapter Power Switch Characteristics
    8. 6.8  USB Endpoint Requirements and Characteristics
    9. 6.9  Analog-to-Digital Converter (ADC) Characteristics
    10. 6.10 Input/Output (I/O) Requirements and Characteristics
    11. 6.11 I2C Slave Requirements and Characteristics
    12. 6.12 SPI Master Characteristics
    13. 6.13 Single-Wire Debugger (SWD) Timing Requirements
    14. 6.14 ADP_POWER_CFG Configuration Requirements
    15. 6.15 Thermal Shutdown Characteristics
    16. 6.16 Oscillator Requirements and Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adapter Power Switch
        1. 8.3.1.1 Adapter Switch with RSENSE
        2. 8.3.1.2 Adapter Switch without RSENSE
        3. 8.3.1.3 External Current Sense
        4. 8.3.1.4 External Current Limit
        5. 8.3.1.5 Soft Start
        6. 8.3.1.6 ADP_POWER_CFG
      2. 8.3.2  USB Type-C Port Data Multiplexer
        1. 8.3.2.1 USB2.0 Low-Speed Endpoint
      3. 8.3.3  Power Management
        1. 8.3.3.1 Power-On and Supervisory Functions
        2. 8.3.3.2 Supply Switch-Over
        3. 8.3.3.3 RESETZ and MRESET
      4. 8.3.4  Digital Core
      5. 8.3.5  System Glue Logic
      6. 8.3.6  Power Reset Congrol Module (PRCM)
      7. 8.3.7  Interrupt Monitor
      8. 8.3.8  ADC Sense
      9. 8.3.9  I2C Slave
      10. 8.3.10 SPI Master
      11. 8.3.11 Single-Wire Debugger Interface
      12. 8.3.12 ADC
        1. 8.3.12.1 ADC Divider Ratios
        2. 8.3.12.2 ADC Operating Modes
        3. 8.3.12.3 Single Channel Readout
        4. 8.3.12.4 Round Robin Automatic Readout
        5. 8.3.12.5 One Time Automatic Readout
      13. 8.3.13 I/O Buffers
        1. 8.3.13.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 8.3.13.2 IOBUF_OD
        3. 8.3.13.3 IOBUF_I2C
        4. 8.3.13.4 IOBUF_GPIOHSPI
        5. 8.3.13.5 IOBUF_GPIOHSSWD
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Application Code
      5. 8.4.5 Flash Memory Read
      6. 8.4.6 Invalid Flash Memory
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. 8.5.2.1 I2C Interface Description
        2. 8.5.2.2 I2C Clock Stretching
        3. 8.5.2.3 I2C Address Setting
        4. 8.5.2.4 Unique Address Interface
        5. 8.5.2.5 I2C Pin Address Setting
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB4 Device Application with Host Charging
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Power Supply Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 USB Power Delivery Source Capabilities
          2. 9.2.1.2.2 USB Power Delivery Sink Capabilities
          3. 9.2.1.2.3 Supported Data Modes
          4. 9.2.1.2.4 USB4 Hub Controller & PD Controller I2C Communication
          5. 9.2.1.2.5 Dock Management Controller & PD Controller I2C Communication
          6. 9.2.1.2.6 SPI Flash Options
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 1VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 ADP_IN 3.3 V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement
      2. 11.2.2 Recommended Via Size and Trace Widths
      3. 11.2.3 Adapter Input Power Routing
      4. 11.2.4 USB2 Routing
      5. 11.2.5 Oval Pad for BGA Fan Out
      6. 11.2.6 Top and Bottom Layer Complete Routing
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

BALL NAME BALL NUMBER TYPE POR STATE DESCRIPTION
ADP_IN H11, J10, J11, K11 Power N/A Adapter Input to Internal LDO.
ADP_POWER_CFG F10 Analog Input Input (Hi-Z) Sampled by ADC at boot to determine adapter switch behavior.
DBG_USB2_N L7 Analog I/O Hi-Z USB D- Connection for USB Debug.
DBG_USB2_P K7 Analog I/O Hi-Z USB D+ Connection for USB Debug.
EXT_MRESET E11 Digital I/O Hi-Z Forces RESETZ to assert. This pin asserts RESETZ when pulled high. Ground pin with a 1-MΩ resistor when unused in the application.
EXT_RESETZ F11 Digital I/O Push-Pull Output (Low) Active low reset output when VOUT_3V3 is low (driven low on start-up). Float pin when unused.
GND A1, A11, A6, A7, A8, B11, B7, B8, C11, D11, D5, D8, E4, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8, H10, H4, H5, H8, J1, J2, K4, K5, K8, L1, L4, L5, L8 Ground N/A Ground. Connect all balls to ground plane.
GPIO_0(1) B2 Digital I/O Hi-Z General Purpose Digital I/O 0. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_1(1) C2 Digital I/O Hi-Z General Purpose Digital I/O 1. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_2(1) D10 Digital I/O Hi-Z General Purpose Digital I/O 2. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_3(1) G11 Digital I/O Hi-Z General Purpose Digital I/O 3. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_4(1) C10 Digital I/O Hi-Z General Purpose Digital I/O 4. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_5(1) E10 Digital I/O Hi-Z General Purpose Digital I/O 5. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_6(1) G10 Digital I/O Hi-Z General Purpose Digital I/O 6. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_7(1) D7 Digital I/O Hi-Z General Purpose Digital I/O 7. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_8(1) H6 Digital I/O Hi-Z General Purpose Digital I/O 8. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_12(1) K3 Digital I/O Hi-Z General Purpose Digital I/O 12. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_13(1) L3 Digital I/O Hi-Z General Purpose Digital I/O 13. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_14(1) K2 Digital I/O Hi-Z General Purpose Digital I/O 14. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO_15(1) L2 Digital I/O Hi-Z General Purpose Digital I/O 15. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
HRESET D6 Digital Input Hi-Z Active high hardware reset input. Will re-load settings from external flash memory. Ground pin when HRESET functionality will not be used.
HV_GATE1 B9 Analog Output Short to Sense_P External NFET gate control for high voltage power path. Float pin when unused
HV_GATE2 A9 Analog Output Short to ADP_IN External NFET gate control for high voltage power path. Float pin when unused
I2C1_IRQz C1 Digital Output Hi-Z I2C port 1 interrupt. Active low. Implement externally as an open drain with a pullup resistance. Float pin when unused.
I2C1_SCL D2 Digital I/O Digital Input I2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C1_SDA D1 Digital I/O Digital Input I2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C2_IRQz B6 Digital Output Hi-Z I2C port 2 interrupt. Active low. Implement externally as an open drain with a pullup resistance. Float pin when unused.
I2C2_SCL B5 Digital I/O Digital Input I2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C2_SDA A5 Digital I/O Digital Input I2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C_ADDR F1 Analog I/O Analog Input Sets the I2C address for both I2C ports as well as determine the master and slave devices for memory code sharing.
LDO_1V8A K1 Power N/A Output of the 3.3 V or 1.8 V LDO for Core Analog Circuits. Bypass with capacitance CLDO_1V8A to GND.
LDO_1V8D A2 Power N/A Output of the 3.3 V or 1.8 V LDO for Core Digital Circuits. Bypass with capacitance CLDO_1V8D to GND.
LDO_3V3 G1 Power N/A Output of the ADP_IN to 3.3 V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND
LDO_BMC E1 Power N/A Output of the 1.1V output level LDO. Bypass with capacitance CLDO_BMC to GND.
NC E2, F2, K10, K9, L10, L11, L9 Blank N/A Populated Ball that must remain unconnected.
R_OSC G2 Analog I/O Hi-Z External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC.
SENSE_N A10 Analog Input Analog Input Negative sense for external high voltage power path current sense resistance. Short pin to ADP_IN when unused.
SENSE_P B10 Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to ADP_IN when unused.
SPI_CLK A3 Digital Output Digital Input SPI serial clock. Ground pin when unused.
SPI_MISO A4 Digital Input Digital Input SPI serial master input from slave. This pin is used during boot sequence to determine if the flash memory is valid. Ground pin when unused.
SPI_MOSI B4 Digital Output Digital Input SPI serial master output to slave. Ground pin when unused.
SPI_SSz B3 Digital Output Digital Input SPI slave select. Ground pin when unused.
SS H7 Analog Output Driven Low Soft Start. Tie pin to capacitance CSS to ground.
SWD_CLK G4 Digital Input Resistive Pull High SWD serial clock. Float pin when unused.
SWD_DATA F4 Digital I/O Resistive Pull High SWD serial data. Float pin when unused.
UFP_USB2_N L6 Analog I/O Hi-Z USB D- Connection for USB Endpoint.
UFP_USB2_P K6 Analog I/O Hi-Z USB D+ Connection for USB Endpoint.
VDDIO B1 Power N/A VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply input, bypass with capacitance CVDDIO to GND.
VIN_3V3 H1 Power N/A Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
VOUT_3V3 H2 Power N/A Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND. Float pin when unused.
(1) GPIO Function is determined by device firmware. Consult device TRM for available GPIO behaviors.