SLVSFN7 September   2020 TPS65982DMC

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Adapter Power Switch Characteristics
    8. 6.8  USB Endpoint Requirements and Characteristics
    9. 6.9  Analog-to-Digital Converter (ADC) Characteristics
    10. 6.10 Input/Output (I/O) Requirements and Characteristics
    11. 6.11 I2C Slave Requirements and Characteristics
    12. 6.12 SPI Master Characteristics
    13. 6.13 Single-Wire Debugger (SWD) Timing Requirements
    14. 6.14 ADP_POWER_CFG Configuration Requirements
    15. 6.15 Thermal Shutdown Characteristics
    16. 6.16 Oscillator Requirements and Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adapter Power Switch
        1. 8.3.1.1 Adapter Switch with RSENSE
        2. 8.3.1.2 Adapter Switch without RSENSE
        3. 8.3.1.3 External Current Sense
        4. 8.3.1.4 External Current Limit
        5. 8.3.1.5 Soft Start
        6. 8.3.1.6 ADP_POWER_CFG
      2. 8.3.2  USB Type-C Port Data Multiplexer
        1. 8.3.2.1 USB2.0 Low-Speed Endpoint
      3. 8.3.3  Power Management
        1. 8.3.3.1 Power-On and Supervisory Functions
        2. 8.3.3.2 Supply Switch-Over
        3. 8.3.3.3 RESETZ and MRESET
      4. 8.3.4  Digital Core
      5. 8.3.5  System Glue Logic
      6. 8.3.6  Power Reset Congrol Module (PRCM)
      7. 8.3.7  Interrupt Monitor
      8. 8.3.8  ADC Sense
      9. 8.3.9  I2C Slave
      10. 8.3.10 SPI Master
      11. 8.3.11 Single-Wire Debugger Interface
      12. 8.3.12 ADC
        1. 8.3.12.1 ADC Divider Ratios
        2. 8.3.12.2 ADC Operating Modes
        3. 8.3.12.3 Single Channel Readout
        4. 8.3.12.4 Round Robin Automatic Readout
        5. 8.3.12.5 One Time Automatic Readout
      13. 8.3.13 I/O Buffers
        1. 8.3.13.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 8.3.13.2 IOBUF_OD
        3. 8.3.13.3 IOBUF_I2C
        4. 8.3.13.4 IOBUF_GPIOHSPI
        5. 8.3.13.5 IOBUF_GPIOHSSWD
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Application Code
      5. 8.4.5 Flash Memory Read
      6. 8.4.6 Invalid Flash Memory
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. 8.5.2.1 I2C Interface Description
        2. 8.5.2.2 I2C Clock Stretching
        3. 8.5.2.3 I2C Address Setting
        4. 8.5.2.4 Unique Address Interface
        5. 8.5.2.5 I2C Pin Address Setting
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB4 Device Application with Host Charging
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Power Supply Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 USB Power Delivery Source Capabilities
          2. 9.2.1.2.2 USB Power Delivery Sink Capabilities
          3. 9.2.1.2.3 Supported Data Modes
          4. 9.2.1.2.4 USB4 Hub Controller & PD Controller I2C Communication
          5. 9.2.1.2.5 Dock Management Controller & PD Controller I2C Communication
          6. 9.2.1.2.6 SPI Flash Options
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 1VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 ADP_IN 3.3 V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement
      2. 11.2.2 Recommended Via Size and Trace Widths
      3. 11.2.3 Adapter Input Power Routing
      4. 11.2.4 USB2 Routing
      5. 11.2.5 Oval Pad for BGA Fan Out
      6. 11.2.6 Top and Bottom Layer Complete Routing
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1 USB4 Device Application with Host Charging

The figure below shows a USB4 Device application, where there are a total of four Type-C PD Ports. One port is the main connection to a USB4 Host that is a UFP in terms of data and a source of power. The other three ports are DFPs in terms of data and source power. Generally the main UFP source Type-C PD port provides the highest power (up to 100 W) to charge a USB4 Host. The key four devices in the system are the PD Controller (2), Dock Management Controller, USB4 Hub Controller, and UFP Variable Power Supply.

GUID-20200909-CA0I-9QGQ-FV9L-R5G1Z63LTRR2-low.gifFigure 9-1 USB4 Device Block Diagram

In this application, two dual port TPS65988DK PD controllers are used to determine the connection and provide power on the Type-C ports. The primary TPS65988DK manages Port A (UFP Source) and Port B (DFP Source). The secondary TPS65988DK manages the other two, Port C (DFP Source) and Port D (DFP Source). For systems that do not need all four ports a combination of TPS65988DK and TPS65987DDK may be used to scale for specific design requirements. The PD controllers have two I2C clients that are controlled by the Dock Management Controller and the USB4 Hub Controller. The PD controllers have an optional I2C Host that may be used to control a variable power supply.

The Dock Management Controller (DMC), TPS65982DMC, main functions are the Connection Manager, Power Manager, Input Power Control, Secure Firmware Update & booting of the PD controllers. The Connection Manager determines the capabilities of the UFP connection and sets the DFP capabilities accordingly. The Power Manager keeps the power allocated to each of the Type-C ports within a specific power budget and also monitors the entire system power to keep from over loading the Barrel Jack adapter supply. The DMC also controls the input power to the system and soft starts the power path to prevent large inrush currents when the Barrel Jack supply is connected. The Secure Firmware Update is accomplished over USB2, the DMC is connected to one of the USB2 DFP ports on the USB4 Hub Controller or USB2 Hub in the system. The DMC provides the Secure Firmware Update for itself and the PD controllers. The DMC will boot the PD controllers over the I2C connection. The I2C connection between the DMC and PD controllers also serves as communication channel for the Connection and Power Manager.

The USB4 Hub Controller manages the data paths for all of the Type-C ports and determines the required data protocol by reading the PD controller status over I2C connection. The UFP port is the main connection to the USB4 Hub Controller from a USB4 host. The other DFP ports act as expansion ports to connect other USB Type-C & PD devices.

The UFP Variable Power Supply provides 5 V/9 V/15 V/20 V up to 100 W to charge the connected USB4 host. The TPS55288 is used in this application since it is capable of tightly regulating the output voltage and current. The TPS55288 is best connected to the I2C Host on the Primary PD controller, to set the output voltage and current regulation. The other DFP ports generally support 5 V @ 3 A to connect to Type-C & PD devices.