SLVSES1 Data sheet

SLVSES1D May 2018 – October 2022 TPS65987D

PRODUCTION DATA

6.16 SPI Controller Timing Requirements

			MIN	NOM	MAX	UNIT
ƒ_SPI	Frequency of SPI_CLK		11.4	12	12.6	MHz
t_PER	Period of SPI_CLK (1/F_SPI)		79.36	83.33	87.72	ns
t_WHI	SPI_CLK high width		30			ns
t_WLO	SPI_CLK low width		30			ns
t_DACT	SPI_SZZ falling to SPI_CLK rising delay time		30		50	ns
t_DINACT	SPI_CLK falling to SPI_CSZ rising delay time		158		180	ns
t_DPICO	SPI_CLK falling to SPI_PICO Valid delay time		–10		10	ns
t_SUPOCI	SPI_POCI valid to SPI_CLK falling setup time		33			ns
t_HDMSIO	SPI_CLK falling to SPI_POCI invalid hold time		0			ns
t_RIN	SPI_POCI input rise time				5	ns
t_RSPI	SPI_CSZ/CLK/PICO rise time	10% to 90%, C_L = 5 to 50 pF, LDO_3V3 = 3.3 V	1		25	ns
t_FSPI	SPI_CSZ/CLK/PICO fall time	90% to 10%, C_L = 5 to 50 pF, LDO_3V3 = 3.3 V	1		25	ns