SLVSES1D May 2018 – October 2022 TPS65987D
PRODUCTION DATA
When routing the USB2 signals to the TPS65987D BC1.2 detection pins it is recommended to reduce the amount of excess trace to get to the TPS65987D pins, as this will cause antennae and degrade signal integrity. The USB top/bottom signals are shorted together in this example and the same approach can be used if an external USB mux is used. There are several approaches that can be used to get optimal routing; “tap” the USB2 signals with vias that connect the TPS65987D pins, via up to the layer where the pins are located and continue to route on that layer, or a combination of both.
In this layout example, the D+/D- lines are routed to an internal layer from the connector. They are then via’d up to the TPS65987D directly at the pins. There is a small trace that is connecting the via to the pin on the top layer. When routing the D+/D- in this manner, the added stub is minimal.
Figure 11-16 shows the entire routing from the Type-C connector, ESD Protection, and TPS65987D BC1.2 Detection. This example does not take length matching into consideration but It is recommended to follow standard USB2 rules for routing and length matching.