SLVSDB5B July   2018  – August 2021 TPS65988

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Consumption Characteristics
    7. 6.7  Power Switch Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 BC1.2 Characteristics
    11. 6.11 Thermal Shutdown Characteristics
    12. 6.12 Oscillator Characteristics
    13. 6.13 I/O Characteristics
    14. 6.14 PWM Driver Characteristics
    15. 6.15 I2C Requirements and Characteristics
    16. 6.16 SPI Controller Timing Requirements
    17. 6.17 HPD Timing Requirements
    18. 6.18 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
        3. 8.3.2.3 Supply Switch Over
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1 PP_HV Power Switch
          1. 8.3.3.1.1 PP_HV Over Current Clamp
          2. 8.3.3.1.2 PP_HV Over Current Protection
          3. 8.3.3.1.3 PP_HV OVP and UVP
          4. 8.3.3.1.4 PP_HV Reverse Current Protection
        2. 8.3.3.2 Schottky for Current Surge Protection
        3. 8.3.3.3 PP_EXT Power Path Control
        4. 8.3.3.4 PP_CABLE Power Switch
          1. 8.3.3.4.1 PP_CABLE Over Current Protection
          2. 8.3.3.4.2 PP_CABLE Input Good Monitor
        5. 8.3.3.5 VBUS Transition to VSAFE5V
        6. 8.3.3.6 VBUS Transition to VSAFE0V
      4. 8.3.4  Cable Plug and Orientation Detection
        1. 8.3.4.1 Configured as a DFP
        2. 8.3.4.2 Configured as a UFP
        3. 8.3.4.3 Configured as a DRP
        4. 8.3.4.4 Fast Role Swap Signaling
      5. 8.3.5  Dead Battery Operation
        1. 8.3.5.1 Dead Battery Advertisement
        2. 8.3.5.2 BUSPOWER (ADCIN1)
      6. 8.3.6  Battery Charger Detection and Advertisement
        1. 8.3.6.1 BC1.2 Data Contact Detect
        2. 8.3.6.2 BC1.2 Primary and Secondary Detection
        3. 8.3.6.3 Charging Downstream Port Advertisement
        4. 8.3.6.4 Dedicated Charging Port Advertisement
        5. 8.3.6.5 2.7V Divider3 Mode Advertisement
        6. 8.3.6.6 1.2V Mode Advertisement
        7. 8.3.6.7 DCP Auto Mode Advertisement
      7. 8.3.7  ADC
      8. 8.3.8  DisplayPort HPD
      9. 8.3.9  Digital Interfaces
        1. 8.3.9.1 General GPIO
        2. 8.3.9.2 I2C
        3. 8.3.9.3 SPI
      10. 8.3.10 PWM Driver
      11. 8.3.11 Digital Core
      12. 8.3.12 I2C Interfaces
        1. 8.3.12.1 I2C Interface Description
        2. 8.3.12.2 I2C Clock Stretching
        3. 8.3.12.3 I2C Address Setting
        4. 8.3.12.4 Unique Address Interface
        5. 8.3.12.5 I2C Pin Address Setting (ADCIN2)
      13. 8.3.13 SPI Controller Interface
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot
      2. 8.4.2 Power States
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Type-C VBUS Design Considerations
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External Sink Power Path Options
            1. 9.2.1.2.1.1 Load Switch Power Path
            2. 9.2.1.2.1.2 Discrete Power Path
          2. 9.2.1.2.2 Type-C Connector VBUS Capacitors
          3. 9.2.1.2.3 VBUS Schottky and TVS Diodes
          4. 9.2.1.2.4 VBUS Snubber Circuit
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual Port Thunderbolt Notebook with AR Supporting USB PD Charging
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 USB Power Delivery Source Capabilities
        3. 9.2.2.3 USB Power Delivery Sink Capabilities
        4. 9.2.2.4 Supported Data Modes
        5. 9.2.2.5 RESETN
        6. 9.2.2.6 I2C Design Requirements
        7. 9.2.2.7 TS3DS10224 SBU Mux for AUX and LSTX/RX
        8. 9.2.2.8 Thunderbolt Flash Options
      3. 9.2.3 Dual Port USB & Displayport Notebook Supporting PD Charging
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 USB Power Delivery Source Capabilities
        3. 9.2.3.3 USB Power Delivery Sink Capabilities
        4. 9.2.3.4 Supported Data Modes
        5. 9.2.3.5 TUSB1044 Re-Driver GPIO Control
      4. 9.2.4 USB Type-C & PD Monitor/Dock
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 USB Power Delivery Source Capabilities
          2. 9.2.4.2.2 USB and DisplayPort Supported Data Modes
          3. 9.2.4.2.3 TUSB1064 Super Speed Mux GPIO Control
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VBUS 3.3-V LDO
    2. 10.2 1.8-V Power
    3. 10.3 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1  Layout Guidelines
    2. 11.2  Layout Example
    3. 11.3  Stack-Up and Design Rules
    4. 11.4  Main Component Placement
    5. 11.5  1.4 Super Speed Type-C Connectors
    6. 11.6  Capacitor Placement
    7. 11.7  CC1/2 Capacitors & ADCIN1/2 Resistors
    8. 11.8  CC & SBU Protection Placement
    9. 11.9  CC Routing
    10. 11.10 DRAIN1 and DRAIN2 Pad Pours
    11. 11.11 USB2 Routing for ESD Protection and BC1.2
    12. 11.12 VBUS Routing
    13. 11.13 Completed Layout
    14. 11.14 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Firmware Warranty Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-28171F38-42B9-406E-B586-B104D3049BCA-low.gif Figure 5-1 RSH Package56-Pin QFNTop View
Table 5-1 Pin Functions
PIN TYPE(2) RESET STATE(1) DESCRIPTION
NAME NO.
ADCIN1 6 I Input Boot configuration Input. Connect to resistor divider between LDO_3V3 and GND.
ADCIN2 10 I Input I2C address configuration Input. Connect to resistor divider between LDO_3V3 and GND.
C1_CC1 24 I/O High-Z Output to Type-C CC or VCONN pin for port 1. Filter noise with capacitor to GND
C1_CC2 26 I/O High-Z Output to Type-C CC or VCONN pin for port 1. Filter noise with capacitor to GND
C1_USB_N (GPIO19) 53 I/O Input (High-Z) Port 1 USB D– connection for BC1.2 support
C1_USB_P (GPIO18) 50 I/O Input (High-Z) Port 1 USB D+ connection for BC1.2 support
C2_CC1 45 I/O High-Z Output to Type-C CC or VCONN pin for port 2. Filter noise with capacitor to GND
C2_CC2 47 I/O High-Z Output to Type-C CC or VCONN pin for port 2. Filter noise with capacitor to GND
C2_USB_N (GPIO21) 55 I/O Input (High-Z) Port 2 USB D– connection for BC1.2 support
C2_USB_P (GPIO20) 54 I/O Input (High-Z) Port 2 USB D+ connection for BC1.2 support
DRAIN1 8, 15, 19, 58 — — Drain of internal power path 1. Connect thermal pad 58 to as big of pad as possible on PCB for best thermal performance. Short the other pins to this thermal pad
DRAIN2 7, 52, 56, 57 — — Drain of internal power path 2. Connect thermal pad 57 to as big of pad as possible on PCB for best thermal performance. Short the other pins to this thermal pad
GND 20, 51 — — Unused pin. Tie to GND.
GPIO0 16 I/O Input (High-Z) General Purpose Digital I/O 0. Float pin when unused. GPIO0 is asserted low during the TPS65988 boot process. Once device configuration and patches are loaded GPIO0 is released
GPIO1 17 I/O Input (High-Z) General Purpose Digital I/O 1. Ground pin with a 1-MΩ resistor when unused in the application
GPIO2 18 I/O Input (High-Z) General Purpose Digital I/O 2. Float pin when unused
GPIO3 (HPD1) 30 I/O Input (High-Z) General Purpose Digital I/O 3. Configured as Hot Plug Detect (HPD) TX and RX for port 1 when DisplayPort alternate mode is enabled. Float pin when unused
GPIO4 (HPD2) 31 I/O Input (High-Z) General Purpose Digital I/O 4. Configured as Hot Plug Detect (HPD) TX and RX for port 2 when DisplayPort alternate mode is enabled. Float pin when unused
I2C3_SCL (GPIO5) 21 I/O Input (High-Z) I2C port 3 serial clock. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used. Float pin when unused
I2C3_SDA (GPIO6) 22 I/O Input (High-Z) I2C port 3 serial data. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used. Float pin when unused
I2C3_IRQ (GPIO7) 23 I/O Input (High-Z) I2C port 3 interrupt detection (port 3 operates as an I2C Master Only). Active low detection. Connect to the I2C slave's interrupt line to detect when the slave issues an interrupt. Float pin when unused
GPIO12 40 I/O Input (High-Z) General Purpose Digital I/O 12. Float pin when unused
GPIO13 41 I/O Input (High-Z) General Purpose Digital I/O 13. Float pin when unused
GPIO14 (PWM) 42 I/O Input (High-Z) General Purpose Digital I/O 14. May also function as a PWM output. Float pin when unused
GPIO15 (PWM) 43 I/O Input (High-Z) General Purpose Digital I/O 15. May also function as a PWM output. Float pin when unused
GPIO16 (PP_EXT1) 48 I/O Input (High-Z) General Purpose Digital I/O 16. May also function as single wire enable signal for external power path 1. Pull-down with external resistor when used for external path control. Float pin when unused
GPIO17 (PP_EXT2) 49 I/O Input (High-Z) General Purpose Digital I/O 17. May also function as single wire enable signal for external power path 2. Pull-down with external resistor when used for external path control. Float pin when unused
HRESET 44 I/O Input Active high hardware reset input. Will reinitialize all device settings. Ground pin when HRESET functionality will not be used
I2C1_IRQ 29 O High-Z I2C port 1 interrupt. Active low. Implement externally as an open drain with a pull-up resistance. Float pin when unused
I2C1_SCL 27 I/O High-Z I2C port 1 serial clock. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used or unused
I2C1_SDA 28 I/O High-Z I2C port 1 serial data. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used or unused
I2C2_IRQ 34 O High-Z I2C port 2 interrupt. Active low. Implement externally as an open drain with a pull-up resistance. Float pin when unused
I2C2_SCL 32 I/O High-Z I2C port 2 serial clock. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used or unused
I2C2_SDA 33 I/O High-Z I2C port 2 serial data. Open-drain output. Tie pin to I/O voltage through a 10-kΩ resistance when used or unused
LDO_1V8 35 PWR — Output of the 1.8-V LDO for internal circuitry. Bypass with capacitor to GND
LDO_3V3 9 PWR — Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitor to GND
PP1_CABLE 25 PWR — 5-V supply input for port 1 C_CC pins. Bypass with capacitor to GND
PP2_CABLE 46 PWR — 5-V supply input for port 2 C_CC pins. Bypass with capacitor to GND
PP_HV1 11, 12 PWR — System side of first VBUS power switch. Bypass with capacitor to ground. Tie to ground when unused
PP_HV2 1, 2 PWR — System side of second VBUS power switch. Bypass with capacitor to ground. Tie to ground when unused
SPI_CLK 38 I/O Input SPI serial clock. Ground pin when unused
SPI_POCI 36 I/O Input SPI serial controller input from peripheral. Ground pin when unused
SPI_PICO 37 I/O Input SPI serial controller output to peripheral. Ground pin when unused
SPI_CS 39 I/O Input SPI chip select. Ground pin when unused
VBUS1 13, 14 PWR — Port side of first VBUS power switch. Bypass with capacitor to ground.
VBUS2 3, 4 PWR — Port side of second VBUS power switch. Bypass with capacitor to ground.
VIN_3V3 5 PWR — Supply for core circuitry and I/O. Bypass with capacitor to GND
Thermal Pad (PPAD) 59 GND — Ground reference for the device as well as thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad must be connected to a ground plane
(1) Reset State indicates the state of a given pin immediately following power application, prior to any configuration from firmware.
(2) I = input, O = output, I/O = bidirectional, GND = ground, PWR = power, NC = no connect