SGLS272I october   2004  – may 2023 TPS715-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4.     Thermal Information
    5. 6.4 Electrical Characteristics
    6. 6.5 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Wide Supply Range
      2. 7.3.2 Low Quiescent Current
      3. 7.3.3 Dropout Voltage (VDO)
      4. 7.3.4 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Programming the TPS71501-Q1 Adjustable LDO Regulator
        2. 8.2.1.2 External Capacitor Requirements
        3. 8.2.1.3 Input and Output Capacitor Requirements
        4. 8.2.1.4 Reverse Current
        5. 8.2.1.5 Feed-Forward Capacitor (CFF)
        6. 8.2.1.6 Power Dissipation (PD)
        7. 8.2.1.7 Estimating Junction Temperature
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Power Dissipation
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCK|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature.

Equation 9. TJ = TT + ψJT × PD

where:

  • PD is the dissipated power
  • TT is the temperature at the center-top of the device package
Equation 10. TJ = TB + ψJB × PD

where:

  • TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note.