SGLS272I october 2004 – may 2023 TPS715-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIN | Input voltage (1) | IO = 10 mA | 2.5 | 24 | V | ||
IO = 50 mA | 3 | 24 | |||||
VOUT | Output voltage range (TPS71501) | 1.205 | 15 | V | |||
Output voltage accuracy (1)(2) | VOUT + 1 V ≤ VIN ≤ 24 V, 100 µA ≤ IOUT ≤ 50 mA |
–4 | 4 | % | |||
IGND | Ground pin current (legacy chip)(3) | 0 ≤ IOUT ≤ 50 mA , TJ = –40°C to 85°C | 3.2 | 4.2 | μA | ||
0 mA ≤ IOUT ≤ 50 mA | 3.2 | 4.8 | |||||
0 mA ≤ IOUT ≤ 50 mA , VIN = 24 V | 5.8 | ||||||
Ground pin current (new chip) (3) | 0 ≤ IOUT ≤ 50 mA , TJ = –40°C to 85°C | 3.2 | 4.1 | ||||
0 mA ≤ IOUT ≤ 50 mA | 3.2 | 4.3 | |||||
0 mA ≤ IOUT ≤ 50 mA , VIN = 24 V | 4.5 | ||||||
ΔVOUT(ΔIOUT) | Load regulation | IOUT = 100 μA to 50 mA | 22 | mV | |||
ΔVOUT(ΔVIN) | Output voltage line regulation (legacy chip) (1) | VOUT(NOM) + 1 V ≤ VIN ≤ 24 V | 20 | 60 | mV | ||
Output voltage line regulation (new chip) (1) | VOUT(NOM) + 1 V ≤ VIN ≤ 24 V | 20 | 22 | ||||
Vn | Output noise voltage (legacy chip) (4) | BW = 200 Hz to 100 kHz, COUT = 10 μF, IOUT = 50 mA |
575 | μVrms | |||
Output noise voltage (new chip)(4) | BW = 200 Hz to 100 kHz, COUT = 10 μF, IOUT = 50 mA |
425 | |||||
ICL | Output current limit (legacy chip) | VOUT = 0 V, VIN ≥ 3.5 V | 125 | 750 | mA | ||
VOUT = 0 V, VIN < 3.5 V | 90 | 750 | |||||
Output current limit (new chip) | VOUT = 0 V, VIN ≥ 3.5 V | 125 | 350 | ||||
VOUT = 0 V, VIN < 3.5 V | 90 | 350 | |||||
PSRR | Power-supply ripple rejection | f = 100 kHz, COUT = 10 μF | 60 | dB | |||
VDO | Dropout voltage (legacy chip) | IOUT = 50 mA, VIN = VOUT(nom) – 0.1 V | 415 | 750 | mV | ||
Dropout voltage (new chip) | 415 | 525 |