SBVS047I April   2004  – November 2023 TPS715A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Wide Supply Range
      2. 6.3.2 Low Supply Current
      3. 6.3.3 Current Limit
      4. 6.3.4 Dropout Voltage (VDO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting VOUT for the TPS715A01 Adjustable LDO
        2. 7.2.2.2 External Capacitor Requirements
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Power Dissipation
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRV|6
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-20230804-SS0I-B8FD-6SDM-FMCJ3PSGHQK4-low.svgFigure 4-1 DRV Package,6-Pin WSON(Top View)
GUID-20230804-SS0I-PL5M-WXH3-TQJDPTRLJJZ4-low.svgFigure 4-2 DRB Package,8-Pin VSON(Top View)
Table 4-1 Pin Functions
NAME VSON WSON I/O DESCRIPTION
FIXED ADJ. FIXED ADJ.
FB — 5 — 4 I In the adjustable configuration, this pin sets the output voltage with the help of the external feedback divider.
GND 4, Pad 4, Pad 3, Pad 3, Pad — Ground pin.
IN 1 1 1 1 I Input supply pin. Use a capacitor with a value of 0.1 µF or larger from this pin to ground. See the Input and Output Capacitor Requirements section for more information.
NC 2, 3, 5, 6, 7 2, 3, 6, 7 2, 4, 5 2, 5 — No connect pin. This pin is not connected internally. Connect this pin to ground for best thermal performance, or leave floating.
OUT 8 8 6 6 O Output of the regulator. For the new chip, a capacitor with a value of 1 µF or larger is required from this pin to ground.(1) See the Input and Output Capacitor Requirements section for more information.
(1) The nominal output capacitance must be greater than 0.47 µF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 0.47 µF. The legacy chip is stable for any capacitor value ≥ 0.47 μF.