SBVS047I April   2004  – November 2023 TPS715A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Wide Supply Range
      2. 6.3.2 Low Supply Current
      3. 6.3.3 Current Limit
      4. 6.3.4 Dropout Voltage (VDO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting VOUT for the TPS715A01 Adjustable LDO
        2. 7.2.2.2 External Capacitor Requirements
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Power Dissipation
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRV|6
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1 V, IOUT = 1 mA, and COUT = 1 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage (1) IO = 10 mA 2.5 24 V
IO =  80mA 3 24
VOUT Output voltage range (TPS715A01) [legacy chip] 1.2 15 V
Output voltage range (TPS715A01) [new chip] 1.205 15
VOUT Output voltage accuracy (1) TPS715A01 (legacy chip) VOUT + 1 V ≤ VIN ≤ 24 V, 1.2 V ≤ VOUT  ≤ 15 V, 0 ≤ IOUT  ≤ 80 mA –4 4 %
TPS715A01 (new chip) VOUT + 1 V ≤ VIN ≤ 24 V, 1.205 V ≤ VOUT  ≤ 15 V, 0 ≤ IOUT  ≤ 80 mA –4 4
TPS715A33 (legacy chip) 4.3 V ≤ VIN ≤ 24 V, 0 ≤ IOUT  ≤ 80 mA 3.135 3.3 3.465 V
TPS715A33 (new chip) 4.3 V ≤ VIN ≤ 24 V, 0 ≤ IOUT  ≤ 80 mA 3.168 3.3 3.432
IGND Ground pin current (legacy chip) (3) 0 ≤ IOUT ≤  80mA, TJ = –40°C to 85°C 3.2 4.1 μA
0 mA ≤ IOUT ≤  80mA  3.2 4.3
0 mA ≤ IOUT ≤  80mA, VIN = 24 V 4.5
Ground pin current (new chip) (3) 0 ≤ IOUT ≤  80mA, TJ = –40°C to 85°C 3.2 4.2
0 mA ≤ IOUT ≤  80mA  3.2 4.8
0 mA ≤ IOUT ≤  80mA, VIN = 24 V 5.8
ΔVOUT(ΔIOUT) Load regulation IOUT = 100 μA to 80 mA 35 mV
ΔVOUT(ΔVIN) Output voltage line regulation (legacy chip)  (1) VOUT(NOM) + 1 V ≤ VIN ≤ 24 V 20 60 mV
Output voltage line regulation (new chip)  (1) VOUT(NOM) + 1 V ≤ VIN ≤ 24 V 20 22
Vn Output noise voltage (legacy chip) (4)  BW = 200 Hz to 100 kHz,
COUT = 10 μF, IOUT = 50 mA		 575 μVrms
Output noise voltage (new chip)(4)  BW = 200 Hz to 100 kHz,
COUT = 10 μF, IOUT = 50 mA		 425
ICL Output current limit (legacy chip)  VOUT = 0 V 160 1100 mA
Output current limit (new chip)  VOUT = 0 V, VIN ≥ 3.5 V 160 500
Output current limit (new chip)  VOUT = 0 V, VIN < 3.5 V 90 500
PSRR Power-supply ripple rejection (legacy chip) f = 100 kHz, COUT = 10 μF 60 dB
Power-supply ripple rejection (new chip) 60
VDO Dropout voltage (legacy chip)  VIN = VOUT(nom) – 0.1 V, IOUT = 80 mA 670 1120 mV
Dropout voltage (new chip) 650 900
(1) Minimum VIN = VOUT + VDO or the value shown for Input voltage in this table, whichever is greater.
(2) This device employs a leakage null control circuit. This circuit is active only if output current is less than pass transistor leakage current. The circuit is typically active when output load is less than 5 μA, VIN is greater than 18 V, and die temperature is greater than 100°C.
(3) See the Device Nomenclaturesection for details about new and legacy chip descriptions.