SBVS100E June   2008  – September 2015 TPS720

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Inrush Current Limit
      3. 7.3.3 Shutdown
      4. 7.3.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Requirements
      2. 8.1.2 Output Regulation With IN Pin Floating
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Transient Response
      5. 8.1.5 Minimum Load
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Mounting

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DRV Package
6-Pin SON With Exposed Thermal Pad
Top View
TPS720 po_drv_bvs100.gif
1. TI recommends connecting the SON (DRV) package thermal pad to ground.
YZU Package
5-Pin DSBGA
Top View
TPS720 po_yzu_bvs100.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DRV YZU
OUT 1 A3 O Output pin. A 2.2-μF ceramic capacitor is connected from this pin to ground, for stability and to provide load transients. See Input and Output Capacitor Requirements.
NC 2 — — No connection.
EN 3 C3 I Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT. A logic low on this pin turns off the device.
BIAS 4 C1 I Bias supply pin. TI recommends bypassing this input with a ceramic capacitor to ground for better transient performance. See Input and Output Capacitor Requirements.
GND 5 B2 — Ground pin.
IN 6 A1 I Input pin. This pin can be a maximum of 4.5 V; VIN must not exceed VBIAS. Bypass this input with a ceramic capacitor to ground. See Input and Output Capacitor Requirements.