Refer to the PDF data sheet for device specific package drawings
The TPS727 family of low-dropout (LDO) linear regulators are ultralow quiescent current LDOs with excellent line and ultra-fast load transient performance and are designed for power-sensitive applications. The LDO output voltage level is preset by the use of innovative factory EEPROM programming. A precision band-gap and error amplifier provides overall 2% accuracy over load, line, and temperature extremes. The TPS727 family is available in 1.5-mm × 1.5-mm SON and wafer chip-scale (WCSP) packages that make the devices ideal for handheld applications. This family of devices is fully specified over a temperature range of TJ = –40°C to +125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS727xxDSE | WSON (6) | 1.50 mm × 1.50 mm |
TPS727xxYFF | DSBGA (4) | 1.20 mm × 0.80 mm |
Changes from E Revision (September 2014) to F Revision
Changes from D Revision (February 2014) to E Revision
Changes from C Revision (January, 2011) to D Revision
Changes from B Revision (April, 2010) to C Revision
Changes from A Revision (September, 2009) to B Revision
NOTE
The EN pin is marked with a dot for the 1.5-V, 1.8-V, 2.8-V, and 4.8-V versions of the YFF package. The GND pin is marked with a dot for all other voltage versions of the YFF package. Refer to YFF0004 Package Outline page included at the end of this document for dimensions of the YFF package. On the package outline, the shaded box indicates the location of ball A1 and does not correlate to any marking on the topside of the physical package.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage range, VIN | –0.3 | +6.0 | V | |
Enable voltage range, VEN | –0.3 | +6.0(2) | V | |
Output voltage range, VOUT | –0.3 | +6.0 | V | |
Maximum output current, IOUT | Internally limited | |||
Output short-circuit duration | Indefinite | |||
Operating junction temperature, TJ | –55 | +150 | °C | |
Storage temperature, Tstg | –55 | +150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input voltage | 2 | 5.5 | V | |
IOUT | Output current | 0 | 250 | mA | |
TJ | Operating junction temperature range | –40 | +125 | °C |
THERMAL METRIC(1) | TPS727 | UNITS | ||
---|---|---|---|---|
DSE (WSON) | YFF (DSBGA) | |||
6 PINS | 4 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 190.5 | 160 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 94.9 | 75 | °C/W |
RθJB | Junction-to-board thermal resistance | 149.3 | 76 | °C/W |
ψJT | Junction-to-top characterization parameter | 6.4 | 3 | °C/W |
ψJB | Junction-to-board characterization parameter | 152.8 | 74 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance(2) | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VIN | Input voltage range | 2.0 | 5.5 | V | ||||
VO | Output voltage range | 0.9 | 5.0 | V | ||||
VOUT (1) | DC output accuracy | TJ = +25°C | –2.5 | +2.5 | mV | |||
VOUT + 0.3 V ≤ VIN ≤ 5.5 V, 0 mA ≤ IOUT ≤ 200 mA |
–2.0% | ±1.0% | +2.0% | |||||
VOUT + 0.3 V ≤ VIN ≤ 5.5 V, 0 mA ≤ IOUT ≤ 250 mA |
±1.0% | |||||||
ΔVOUT | Load transient | 1 mA to 200 mA or 200 mA to 1 mA in 1 μs, COUT = 1 μF |
±50.0 | mV | ||||
1 mA to 250 mA or 250 mA to 1 mA in 1 μs, COUT = 1 μF |
±65 | |||||||
ΔVO/ΔVIN | Line regulation | VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA |
8 | μV/V | ||||
ΔVO/ΔIOUT | Load regulation | 0 mA ≤ IOUT ≤ 250 mA | 20 | μV/mA | ||||
VDO | Dropout voltage(2) | VIN = 0.98 × VOUT(NOM), IOUT = 10 mA | 6.5 | mV | ||||
VIN = 0.98 × VOUT(NOM), IOUT = 50 mA | 32.5 | |||||||
VIN = 0.98 × VOUT(NOM), IOUT = 100 mA | 65 | |||||||
VIN = 0.98 × VOUT(NOM), IOUT = 200 mA | 130 | 200 | ||||||
VIN = 0.98 × VOUT(NOM), IOUT = 250 mA | 162.5 | |||||||
ICL | Output current limit | VOUT = 0.9 × VOUT(NOM) | 300 | 400 | 550 | mA | ||
IGND | Ground pin current | IOUT = 0 mA, TJ = –40°C to +125°C | 7.9 | 12 | µA | |||
IOUT = 200 mA | 110 | |||||||
IOUT = 250 mA | 130 | |||||||
ISHDN | Shutdown current (IGND) | VEN ≤ 0.4 V, VIN = 2 V, TJ = +25°C | 0.12 | µA | ||||
VEN ≤ 0.4 V, 2.0 V < VIN ≤ 4.5 V, TJ = –40°C to +85°C |
0.55 | 2 | ||||||
PSRR | Power-supply rejection ratio | VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA |
f = 10 Hz | 85 | dB | |||
f = 100 Hz | 75 | |||||||
f = 1 kHz | 70 | |||||||
f = 10 kHz | 55 | |||||||
f = 100 kHz | 40 | |||||||
f = 1 MHz | 45 | |||||||
VN | Output noise voltage | BW = 100 Hz to 100 kHz, VIN = 2.1 V, VOUT = 1.8 V, IOUT = 10 mA |
33.5 | μVRMS | ||||
tSTR | Startup time(3) | COUT = 1.0 μF, 0 ≤ IOUT ≤ 250 mA | 100 | μs | ||||
VHI | Enable pin high (enabled) | 0.9 | VIN | V | ||||
VLO | Enable pin low (disabled) | 0 | 0.4 | V | ||||
IEN | Enable pin current | EN = 5.5 V | 40 | 500 | nA | |||
UVLO | Undervoltage lock-out | VIN rising | 1.85 | 1.90 | 1.95 | V | ||
TSD | Thermal shutdown temperature | Shutdown, temperature increasing | +160 | °C | ||||
Reset, temperature decreasing | +140 | |||||||
TJ | Operating junction temperature | –40 | +125 | °C |
IOUT = 10 mA |
0 mA ≤ IOUT ≤ 10 mA |
VIN = 2.3 V, tR = tF = 1 µs |
Slew rate = 1 V/µs, IOUT = 200 µA |
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 200 mA |
IOUT = 200 mA |
IOUT = 0 mA |
VIN = 2.1 V, IOUT = 0 mA |
IOUT = 10 mA, CIN = COUT = 1 µF |
VIN = 2.3 V, tR = tF = 1 µs |
Slew rate = 1 V/µs, IOUT = 100 µA |
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 100 µA |
IOUT = 200 mA |
The TPS727 devices belong to a family of LDO regulators that consume extremely low quiescent current while simultaneously delivering excellent PSRR with very little headroom (VIN – VOUT differential voltage), and very good transient response. These features, combined with low noise without a noise reduction pin in an ultrasmall package, make these devices ideal for portable applications. This family of regulators offers sub-band-gap output voltages, current limit and thermal protection, and is fully specified from –40°C to +125°C.
The TPS727 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device is turned off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Protection section for more details.
The PMOS pass element in the TPS727 has a built-in body diode that conducts current when the voltage at the OUT pin exceeds the voltage at the IN pin. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current is recommended.
The startup current is given by Equation 1:
Equation 1 shows that soft-start current is directly proportional to COUT.
The output voltage ramp rate is independent of COUT and load current, and has a typical value of 0.07 V/μs.
The TPS727 automatically adjusts the soft-start current to supply both the load current and the COUT charge current. For example, if ILOAD = 0 mA upon enabling the LDO, ISOFT START = 1 μF × 0.07 V/μs + 0 mA = 70 mA, the current that charges the output capacitor.
If ILOAD = 200 mA, ISOFT START = 1 μF × 0.07 V/μs + 200 mA = 270 mA, the current required for charging output capacitor and supplying the load current.
If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, the current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, 10 μF × 0.07 V/μs + 200 mA = 900 mA is not supplied. Instead, the current is clamped at 400 mA.
The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to the IN pin.
The TPS727 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device functions like a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is illustrated in Figure 15 in the Typical Characteristics section.
The TPS727 uses an undervoltage lock-out circuit that keeps the output shut off until the input voltage reaches the UVLO threshold voltage.
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, limit junction temperature to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection triggers at least +35°C above the maximum expected ambient condition of a particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS727 is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the TPS727 into thermal shutdown degrades device reliability.
Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode, thus reducing the operating current to 120 nA, nominal.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS727 family of low-dropout (LDO) linear regulators are utralow quiescent current LDOs with excellent line and ultra-fast load transient performance and are designed for power-sensitive applications.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to
1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.
The TPS727 is designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR must be less than 200 mΩ.
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but increases duration of the transient response.
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to include dropout and output current to account for the GND pin current and to power the load.
Select adequate input and output capacitors.
The startup current is given by Equation 2:
Equation 2 shows that soft-start current is directly proportional to COUT.
The output voltage ramp rate is independent of COUT and load current and has a typical value of 0.07 V/μs.
The TPS727 automatically adjusts the soft-start current to supply both the load current and the COUT charge current. For example, if ILOAD = 0 mA upon enabling the LDO, ISOFT START = 1 μF × 0.07 V/μs + 0 mA = 70 mA, the current that charges the output capacitor.
If ILOAD = 200 mA, ISOFT START = 1 μF × 0.07 V/μs + 200 mA = 270 mA, the current required for charging output capacitor and supplying the load current.
If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, the current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, 10 μF × 0.07 V/μs + 200 mA = 900 mA is not supplied. Instead, the current is clamped at 400 mA.
VIN = 2.3 V, tR = tF = 1 µs |
VIN = 2.3 V, tR = tF = 1 µs |
Slew rate = 1 V/µs, IOUT = 200 µA |
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 200 mA |
IOUT = 10 mA, CIN = COUT = 1 µF |
VIN = 2.3 V, tR = tF = 1 µs |
Slew rate = 1 V/µs, IOUT = 100 µA |
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 100 µA |
IOUT = 200 mA |
Do place at least one 1.0-µF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
For DSE devices, do tie the NC pins to ground to improve thermal dissipation.
Do connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator.
Do not exceed the absolute maximum ratings.