SGLS303G May   2005  – December 2024 TPS732-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Internal Current Limit
      2. 6.3.2 Shutdown
      3. 6.3.3 Dropout Voltage
      4. 6.3.4 Transient Response
      5. 6.3.5 Reverse Current
      6. 6.3.6 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Output Noise
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Power Dissipation
      4. 7.4.4 Package Mounting
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Typical Characteristics

for all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF (unless otherwise noted)

TPS732-Q1 Load Regulation
Legacy silicon 
Figure 5-1 Load Regulation
TPS732-Q1 Line Regulation
Legacy silicon 
Figure 5-3 Line Regulation
TPS732-Q1 Dropout Voltage vs Output Current
Legacy silicon 
Figure 5-5 Dropout Voltage vs Output Current
TPS732-Q1 Dropout Voltage vs Temperature
Legacy silicon 
Figure 5-7 Dropout Voltage vs Temperature
TPS732-Q1 Output Voltage Accuracy Histogram
Legacy silicon 
Figure 5-9 Output Voltage Accuracy Histogram
TPS732-Q1 Ground Pin Current vs Output Current
Legacy silicon 
Figure 5-11 Ground Pin Current vs Output Current
TPS732-Q1 Ground Pin Current vs Temperature
Legacy silicon 
Figure 5-13 Ground Pin Current vs Temperature
TPS732-Q1 Current Limit vs VOUT (FOLDBACK)
Legacy silicon 
Figure 5-15 Current Limit vs VOUT (FOLDBACK)
TPS732-Q1 Ground Pin Current in Shutdown vs Temperature
Legacy silicon 
Figure 5-17 Ground Pin Current in Shutdown vs Temperature
TPS732-Q1 Current Limit vs VIN
Legacy silicon 
Figure 5-19 Current Limit vs VIN
TPS732-Q1 Current Limit vs Temperature
Legacy silicon 
Figure 5-21 Current Limit vs Temperature
TPS732-Q1 PSRR (Ripple Rejection) vs Frequency
Legacy silicon 
Figure 5-23 PSRR (Ripple Rejection) vs Frequency
TPS732-Q1 PSRR (Ripple Rejection) vs VIN – VOUT
Legacy silicon 
Figure 5-25 PSRR (Ripple Rejection) vs VIN – VOUT
TPS732-Q1 Noise Spectral Density vs CNR = 0 μF
Legacy silicon 
Figure 5-27 Noise Spectral Density vs CNR = 0 μF
TPS732-Q1 Noise Spectral Density vs CNR = 0.01 μF
Legacy silicon 
Figure 5-29 Noise Spectral Density vs CNR = 0.01 μF
TPS732-Q1 RMS Noise Voltage vs COUT
Legacy silicon 
Figure 5-31 RMS Noise Voltage vs COUT
TPS732-Q1 RMS Noise Voltage vs CNR
Legacy silicon 
Figure 5-33 RMS Noise Voltage vs CNR
TPS732-Q1 TPS73233-Q1 – Load Transient Response
Legacy silicon 
Figure 5-35 TPS73233-Q1 – Load Transient Response
TPS732-Q1 TPS73233-Q1 – Line Transient Response
Legacy silicon 
Figure 5-37 TPS73233-Q1 – Line Transient Response
TPS732-Q1 TPS73233-Q1 – Turnon Response
Legacy silicon 
Figure 5-39 TPS73233-Q1 – Turnon Response
TPS732-Q1 TPS73233-Q1 – Turnoff Response
Legacy silicon 
Figure 5-41 TPS73233-Q1 – Turnoff Response
TPS732-Q1 TPS73233-Q1 – Power Up and Power Down
Legacy silicon 
Figure 5-43 TPS73233-Q1 – Power Up and Power Down
TPS732-Q1 IENABLE vs Temperature
Legacy silicon 
Figure 5-45 IENABLE vs Temperature
TPS732-Q1 TPS73201-Q1 – RMS Noise Voltage vs CADJ
Legacy silicon 
Figure 5-47 TPS73201-Q1 – RMS Noise Voltage vs CADJ
TPS732-Q1 TPS73201-Q1 – IFB vs Temperature
Legacy silicon 
Figure 5-49 TPS73201-Q1 – IFB vs Temperature
TPS732-Q1 TPS73201-Q1 – Load Transient, Adjustable Version
Legacy silicon 
Figure 5-51 TPS73201-Q1 – Load Transient, Adjustable Version
TPS732-Q1 TPS73201-Q1 – Line Transient, Adjustable Version
Legacy silicon 
Figure 5-53 TPS73201-Q1 – Line Transient, Adjustable Version
TPS732-Q1 Load Regulation
New silicon
Figure 5-2 Load Regulation
TPS732-Q1 Line Regulation
New silicon
Figure 5-4 Line Regulation
TPS732-Q1 Dropout Voltage vs Output Current
New silicon
Figure 5-6 Dropout Voltage vs Output Current
TPS732-Q1 Dropout Voltage vs Temperature
New silicon
Figure 5-8 Dropout Voltage vs Temperature
TPS732-Q1 Output Voltage Drift Histogram
Legacy silicon 
Figure 5-10 Output Voltage Drift Histogram
TPS732-Q1 Ground Pin Current vs Output Current
New silicon
Figure 5-12 Ground Pin Current vs Output Current
TPS732-Q1 Ground Pin Current vs Temperature
New silicon
Figure 5-14 Ground Pin Current vs Temperature
TPS732-Q1 Current Limit vs VOUT (Foldback)
New silicon
Figure 5-16 Current Limit vs VOUT (Foldback)
TPS732-Q1 Ground Pin Current in Shutdown vs Temperature
New silicon
Figure 5-18 Ground Pin Current in Shutdown vs Temperature
TPS732-Q1 Current Limit vs VIN
New silicon
Figure 5-20 Current Limit vs VIN
TPS732-Q1 Current Limit vs Temperature
New silicon
Figure 5-22 Current Limit vs Temperature
TPS732-Q1 PSRR (Ripple Rejection) vs Frequency
New silicon
Figure 5-24 PSRR (Ripple Rejection) vs Frequency
TPS732-Q1 PSRR (Ripple Rejection) vs (VIN – VOUT)
New silicon
Figure 5-26 PSRR (Ripple Rejection) vs (VIN – VOUT)
TPS732-Q1 Noise Spectral Density CNR = 0µF
New silicon
Figure 5-28 Noise Spectral Density CNR = 0µF
TPS732-Q1 Noise Spectral Density CNR = 0.01µF
New silicon
Figure 5-30 Noise Spectral Density CNR = 0.01µF
TPS732-Q1 RMS Noise Voltage vs COUT
New silicon
Figure 5-32 RMS Noise Voltage vs COUT
TPS732-Q1 RMS Noise Voltage vs CNR
New silicon
Figure 5-34 RMS Noise Voltage vs CNR
TPS732-Q1 TPS73233-Q1 Load Transient Response
New silicon
Figure 5-36 TPS73233-Q1 Load Transient Response
TPS732-Q1 TPS73233-Q1 Line Transient Response
New silicon
Figure 5-38 TPS73233-Q1 Line Transient Response
TPS732-Q1 TPS73233-Q1 Turn-On Response
New silicon
Figure 5-40 TPS73233-Q1 Turn-On Response
TPS732-Q1 TPS73233-Q1 Turn-Off Response
New silicon
Figure 5-42 TPS73233-Q1 Turn-Off Response
TPS732-Q1 TPS73233-Q1 Power-Up and Power-Down
New silicon
Figure 5-44 TPS73233-Q1 Power-Up and Power-Down
TPS732-Q1 IENABLE vs Temperature
.
New silicon
Figure 5-46 IENABLE vs Temperature
TPS732-Q1 TPS73201-Q1 RMS Noise Voltage vs CFB
New silicon
Figure 5-48 TPS73201-Q1 RMS Noise Voltage vs CFB
TPS732-Q1 TPS73201-Q1 IFB vs Temperature
New silicon
Figure 5-50 TPS73201-Q1 IFB vs Temperature
TPS732-Q1 TPS73201-Q1 Load Transient, Adjustable Version
New silicon
Figure 5-52 TPS73201-Q1 Load Transient, Adjustable Version
TPS732-Q1 TPS73201-Q1 Line Transient, Adjustable Version
New silicon
Figure 5-54 TPS73201-Q1 Line Transient, Adjustable Version