SGLS303G May   2005  – December 2024 TPS732-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Internal Current Limit
      2. 6.3.2 Shutdown
      3. 6.3.3 Dropout Voltage
      4. 6.3.4 Transient Response
      5. 6.3.5 Reverse Current
      6. 6.3.6 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Output Noise
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Power Dissipation
      4. 7.4.4 Package Mounting
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPS732-Q1 DBV Package5-Pin SOT-23Top ViewFigure 4-1 DBV Package5-Pin SOT-23Top View
TPS732-Q1 DRB Package8-Pin VSON With Exposed Thermal PadTop View
NC: No internal connection
Figure 4-3 DRB Package8-Pin VSON With Exposed Thermal PadTop View
TPS732-Q1 DCQ Package,6-Pin SOT-223(Top View)Figure 4-2 DCQ Package,6-Pin SOT-223
(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
SOT-23 SOT-223 VSON
EN 3 5 5 I Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. See Shutdown for more details. EN can be connected to IN if not used.
FB(2) 4 4 3 I Input to the control loop error amplifier, and is used to set the output voltage of the device.
GND 2 3, 6 4 — Ground
IN 1 1 8 I Unregulated input supply
NR(3) 4 4 3 — Connecting an external capacitor to this pin bypasses noise generated by the internal band gap. This allows output noise to be reduced to low levels.
OUT 5 2 1 O Output of the regulator. There are no output capacitor requirements for stability.
Pad — — Pad — Ground
NC — — 2, 6, 7 — No internal connection
(1) I = Input; O = Output.
(2) Adjustable voltage versions only.
(3) Fixed voltage versions only.