SBVS252B
October 2014 – February 2019
TPS735-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Typical Application
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Internal Current-Limit
7.3.2
Shutdown
7.3.3
Dropout Voltage
7.3.4
Startup and Noise Reduction Capacitor
7.3.5
Transient Response
7.3.6
Undervoltage Lockout (UVLO)
7.3.7
Minimum Load
7.4
Device Functional Modes
7.4.1
Normal Operation
7.4.2
Dropout Operation
7.4.3
Disabled
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Input and Output Capacitor Requirements
8.2.1.2
Feedback Capacitor Requirements (TPS73501-Q1 only)
8.2.2
Detailed Design Procedure
8.2.2.1
Output Noise
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Board Layout Recommendations to Improve PSRR and Noise Performance
10.1.2
Thermal Protection
10.1.3
Package Mounting
10.1.4
Power Dissipation
10.1.5
Estimating Junction Temperature
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Device Nomenclature
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Community Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRB|8
MPDS118K
Thermal pad, mechanical data (Package|Pins)
DRB|8
QFND043N
Orderable Information
sbvs252b_oa
sbvs252b_pm
10.2
Layout Example
1.
C
IN
and C
OUT
are 0603 capacitors and C
NR
is a 0402 capacitor. The footprint is shown to scale with package size.
Figure 25.
TPS735-Q1 Fixed Version Layout Reference Diagram