SBVS252B October   2014  – February 2019 TPS735-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current-Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Dropout Voltage
      4. 7.3.4 Startup and Noise Reduction Capacitor
      5. 7.3.5 Transient Response
      6. 7.3.6 Undervoltage Lockout (UVLO)
      7. 7.3.7 Minimum Load
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input and Output Capacitor Requirements
        2. 8.2.1.2 Feedback Capacitor Requirements (TPS73501-Q1 only)
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Noise
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 10.1.2 Thermal Protection
      3. 10.1.3 Package Mounting
      4. 10.1.4 Power Dissipation
      5. 10.1.5 Estimating Junction Temperature
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.4 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 2.

Equation 2. PD = (VIN – VOUT) × IOUT

NOTE

When the device is used in a condition of high input and low output voltages, PD can exceed the junction temperature rating even when the ambient temperature is at room temperature.

Equation 3 is an example calculation for the power dissipation (PD) of the DRB package.

Equation 3. PD = (6.5 V – 1.2 V) × 500 mA = 2.65 W

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output performance.

On the DRB package, the primary conduction path for heat is through the exposed thermal pad to the PCB. The pad can be connected to ground or left floating; however, the pad must be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum allowable junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device. Use Equation 4 to calculate the maximum junction-to-ambient thermal resistance.

Equation 4. TPS735-Q1 eq_04_slvscd4.gif

Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 22.

TPS735-Q1 ai_theta_ja_slvscd4.gif

NOTE:

The RθJA value at a board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.
Figure 22. RθJA vs Board Size

Figure 22 shows the variation of RθJA as a function of copper area in the board that is connected to the thermal pad. Figure 22 is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and is not to be used to calculate actual thermal performance.

NOTE

When the device is mounted on an application PCB, TI strongly recommends using ΨJT and ΨJB, as explained in the Estimating Junction Temperature section.