SLVSAI3B September   2010  – December 2024 TPS736-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Internal Current Limit
      2. 6.3.2 Transient Response
      3. 6.3.3 Reverse Current
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Enable Pin and Shutdown
      2. 6.4.2 Dropout Voltage
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Application Circuit for Fixed-Voltage Versions
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input And Output Capacitor Requirements
          2. 7.2.1.2.2 Output Noise
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Application Circuit for Adjustable-Voltage Version
        1. 7.2.2.1 Design Requirements
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Example
      2. 7.4.2 Thermal Considerations
      3. 7.4.3 Layout Guidelines
  9. 8 Device And Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, And Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS736-Q1 low-dropout (LDO) linear voltage regulator uses an NMOS topology consisting of an NMOS pass transistor in a voltage-follower configuration. This topology is stable using output capacitors with low ESR, and even allows operation without a capacitor. This topology also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current.

The TPS736-Q1 uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is under 1μA and ideal for portable applications. The extremely low output noise (30μVRMS with 0.1μF CNR) is ideal for powering VCOs. This device is protected by thermal shutdown and foldback current limit.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TPS736-Q1 DBV (SOT-23, 5) 2.9mm × 2.8mm
DCQ (SOT-223, 6) 6.5mm × 7.06mm
(1) For more information, see the Mechanical, Packaging, and Orderable Information.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
TPS736-Q1 Typical Application Typical Application