SLVSAI3B September   2010  – December 2024 TPS736-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Internal Current Limit
      2. 6.3.2 Transient Response
      3. 6.3.3 Reverse Current
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Enable Pin and Shutdown
      2. 6.4.2 Dropout Voltage
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Application Circuit for Fixed-Voltage Versions
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input And Output Capacitor Requirements
          2. 7.2.1.2.2 Output Noise
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Application Circuit for Adjustable-Voltage Version
        1. 7.2.2.1 Design Requirements
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Example
      2. 7.4.2 Thermal Considerations
      3. 7.4.3 Layout Guidelines
  9. 8 Device And Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, And Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF (unless otherwise noted). Typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1)(2) 1.7 5.5 V
VFB Internal reference (TPS73601) TJ = 25°C 1.198 1.204 1.210 V
VOUT Output voltage range (TPS73601)(3) VFB 5.5 - VDO V
Accuracy(1)(4) Nominal  TJ = 25°C –0.5 0.5 %
over VIN, IOUT, and T   VOUT + 0.5V ≤ VIN ≤ 5.5V; 10mA ≤ IOUT ≤ 400mA  –1 ±0.5 1
ΔVOUT(ΔVIN) Line regulation (1) VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V 0.01 %/V
ΔVOUT(ΔIOUT) Load regulation 1mA ≤ IOUT ≤ 400mA 0.002 %/mA
10mA ≤ IOUT ≤ 400mA 0.0005
VDO Dropout voltage(5) (VIN = VOUT(nom) - 0.1V) IOUT = 400mA 75 200 mV
ZO(DO) Output impedance in dropout 1.7V ≤ VIN ≤ VOUT + VDO 0.25 Ω
ICL Output current limit VOUT = 0.9 × VOUT(nom)  legacy silicon 400 650 800 mA
3.6V ≤ VIN ≤ 4.2V, 0℃ ≤ TJ ≤ 70℃ 500 800
VOUT = 0.9 × VOUT(nom)  new silicon  500 800
ISC Short-circuit current VOUT = 0V  450 mA
IREV Reverse leakage current(6) (-IIN) VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT  0.1 10 µA
IGND Ground pin current IOUT = 10mA (IQ)  400 550 µA
IGND Ground pin current IOUT = 400mA   800 1000 µA
ISHDN Shutdown current (IGND) VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5V, –40°C ≤ TJ ≤ 100℃, legacy silicon VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5V, –40°C ≤ TJ ≤ 100℃, legacy silicon 0.02 1.3 µA
ISHDN Shutdown current (IGND) VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5V, new silicon VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5V, new silicon 0.02 1 µA
IFB Feedback pin current (TPS73601) 0.1 0.45 µA
PSRR Power-supply rejection ratio (ripple rejection) f = 100Hz, IOUT = 400mA 58 dB
f = 10kHz, IOUT = 400mA 37
VN Output noise voltage, BW = 10Hz to 100kHz COUT = 10µF, no CNR 27 x VOUT µVRMS
COUT = 10µF, CNR =0.01µF 8.5 x VOUT
tSTR Startup time VOUT = 3V, RL = 30Ω, COUT = 1μF 600 µs
VEN(high) EN pin high (enabled) 1.7 VIN V
VEN(low) EN pin low (shutdown) 0 0.5 V
IEN(high) Enable pin current (enabled) VEN = 5.5V   0.02 0.1 µA
TSD Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
(1) Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.
(2) For VOUT(nom) < 1.6V, when VIN ≤ 1.6V, the output locks to VIN and may result in a damaging over-voltage condition on the output. To avoid this situation, disable the device before powering down VIN. (Legacy silicon only)
(3) TPS73601-Q1 is tested at VOUT = 2.5V.
(4) Tolerance of external resistors not included in this specification.
(5) VDO is not measured for output versions with VOUT(nom) < 1.8V, because minimum VIN = 1.7V.
(6) Fixed-voltage versions only; refer to Application Information section for more information.