SLVSAI3A September   2010  – May 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Transient Response
      3. 7.3.3 Reverse Current
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin and Shutdown
      2. 7.4.2 Dropout Voltage
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Circuit for Fixed-Voltage Versions
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input And Output Capacitor Requirements
          2. 8.2.1.2.2 Output Noise
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application Circuit for Adjustable-Voltage Version
        1. 8.2.2.1 Design Requirements
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
  11. 11Device And Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, And Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

R1 and R2 can be calculated for any output voltage using the formula shown in Figure 34. Sample resistor values for common output voltages are shown in Figure 30.

For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19 kΩ. This 19 kΩ, in addition to the internal 8-kΩ resistor, presents the same impedance to the error amp as the 27-kΩ bandgap reference output. This impedance helps compensate for leakages into the error amp terminals.

8.2 Typical Applications

8.2.1 Typical Application Circuit for Fixed-Voltage Versions

TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 ai_tac_fix_app_bvs038.gif Figure 31. Typical Application Circuit for Fixed-Voltage Versions

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters (Fixed-Voltage Version)

PARAMETER EXAMPLE VALUE
Input voltage 5 V, ±3%
Output voltage 3.3 V, ±1%
Output current 500 mA (maximum), 20 mA (minimum)
RMS noise, 10 Hz to 100 kHz < 30 μVRMS
Ambient temperature 55°C (maximum)

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Input And Output Capacitor Requirements

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1‑μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source.

The TPS736xx-Q1 does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50 nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance meets this requirement.

8.2.1.2.2 Output Noise

A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS736xx-Q1 and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by Equation 3.

Equation 3. TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 Q_Vn_32Vrms-bvs038.gif

Because the value of VREF is 1.2 V, this relationship reduces to Equation 4.

Equation 4. TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 Q_Vn_27Vout_bvs038.gif

for the case of no CNR.

An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF, the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship in Equation 5:

Equation 5. TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 Q_Vn_8_5Vrm-bvs038.gif

for CNR = 10 nF.

This noise reduction effect is shown in Figure 18 in Typical Characteristics.

The TPS73601 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient performance.

The TPS736xx-Q1 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates approximately 250-μV of switching noise at approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT.

8.2.1.3 Application Curves

TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 appcurve_powerup_tps73601.gif Figure 32. TPS73601 Start-Up
TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 appcurve_powerdown_tps73601.gif Figure 33. TPS73601 Shutdown

8.2.2 Typical Application Circuit for Adjustable-Voltage Version

TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 ai_tac_adj_app_bvs038.gif Figure 34. Typical Application Circuit for Adjustable-Voltage Version

8.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 3 as the input parameters.

Table 3. Design Parameters (Adjustable-Voltage Version)

PARAMETER EXAMPLE VALUE
Input voltage 5 V, ±3%, provided by the DC-DC converter switching at 1 MHz
Output voltage 2.5 V, ±1%
Output current 0.4 A (maximum), 10 mA (minimum)
RMS noise, 10 Hz to 100 kHz < 35 μVRMS
Ambient temperature 55°C (maximum)