SLVSER5A December   2018  – May 2021 TPS73801-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable Operation
      2. 7.3.2 Fixed Operation
      3. 7.3.3 Overload Recovery
      4. 7.3.4 Output Voltage Noise
      5. 7.3.5 Protection Features
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Capacitance and Transient Response
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Calculating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

The TPS73801-SEP has an adjustable output voltage range of 1.21 to 20 V. The output voltage is set by the ratio of two external resistors R1 and R2 as shown in Figure 8-1. The device maintains the voltage at the FB pin at 1.21 V referenced to ground. The current in R1 is then equal to (1.21 V / R1), and the current in R2 is the current in R1 plus the FB pin bias current. The FB pin bias current, 3 µA at 25°C, flows through R2 into the FB pin. The output voltage can be calculated using Equation 5.

Equation 5. GUID-875E2313-24D9-4268-B71C-94B98083E6B4-low.gif

The value of R1 should be less than 4.17 kΩ to minimize errors in the output voltage caused by the FB pin bias current. Note that in shutdown the output is turned off, and the divider current is zero. For an output voltage of 2.50 V, R1 will be set to 4.0 kΩ. R2 is then found to be 4.22 kΩ using the equation above.

Equation 6. GUID-E7F90BCE-1A1E-4E4D-B2BE-992930DDC74E-low.gif
Equation 7. VOUT = 2.50 V

The adjustable device is tested and specified with the FB pin tied to the OUT pin for an output voltage of 1.21 V. Specifications for output voltages greater than 1.21 V are proportional to the ratio of the desired output voltage to 1.21 V: VOUT / 1.21 V. For example, load regulation for an output current change of 1 mA to 1.5 A is –2 mV (typ) at VOUT = 1.21 V. At VOUT = 2.50 V, the typical load regulation is:

Equation 8. (2.50 V / 1.21 V)(–2 mV) = –4.13 mV

Figure 8-2 shows the actual change in output is approximately 3 mV for a 1-A load step. The maximum load regulation at 25°C is –8 mV. At VOUT = 2.50 V, the maximum load regulation is:

Equation 9. (2.50 V / 1.21 V)(–8 mV) = –16.53 mV

Since 16.53 mV is 0.7% of the 2.5-V output voltage, the load regulation will meet the design requirements.