SLVSER5A December   2018  – May 2021 TPS73801-SEP

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable Operation
      2. 7.3.2 Fixed Operation
      3. 7.3.3 Overload Recovery
      4. 7.3.4 Output Voltage Noise
      5. 7.3.5 Protection Features
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Capacitance and Transient Response
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Calculating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

  1. For best performance, all traces should be as short as possible.
  2. Use wide traces for IN, OUT, and GND to minimize the parasitic electrical effects.
  3. A minimum output capacitor of 10 µF with an ESR of 3 Ω or less is recommended to prevent oscillations. X5R and X7R dielectrics are preferred.
  4. Place the output capacitor as close as possible to the OUT pin of the device.
  5. The tab of the DCQ package should be connected to ground.