SBVS064O December   2005  – October 2024 TPS74201

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Shutdown
      2. 6.3.2 Power-Good (VQFN Packages Only)
      3. 6.3.3 Internal Current Limit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Output Noise
      5. 7.1.5 Programmable Soft-Start
      6. 7.1.6 Sequencing Requirements
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Protection
      4. 7.4.4 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
      2. 8.2.2 Device Nomenclature
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C, (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 5.5 V
VBIAS BIAS pin voltage range 2.375 5.25 V
VREF Internal reference TJ = 25℃ 0.796 0.8 0.804 V
VOUT Output voltage VIN = 5V, IOUT = 1.5A, VBIAS = 5V  VREF 3.6 V
VOUT Accuracy (1) 2.375V ≤ VBIAS ≤ 5.25V, VOUT + 1.62V ≤ VBIAS 50mA ≤ IOUT ≤ 1.5A -1 ±0.2 1 %
ΔVOUT(ΔVIN) Line regulation VOUT (NOM) + 0.3V ≤ VIN ≤ 5.5V, VQFN 0.0005 0.05 %/V
VOUT (NOM) + 0.3V ≤ VIN ≤ 5.5V, DDPAK/TO-263 0.0005 0.06
ΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 50mA (Legacy Chip) 0.013 %/mA
50 mA ≤ IOUT ≤ 1.5 A (Legacy Chip) 0.04 %/A
50 mA ≤ IOUT ≤ 1.5 A (New Chip) 0.09
VDO VIN dropout voltage(2) IOUT = 1.5 A, VBIAS – VOUT (NOM) ≥ 1.62 V, VQFN  55 100 mV
IOUT = 1.5 A, VBIAS – VOUT (NOM) ≥ 1.62 V, DDPAK/TO-263 (Legacy chip only) 60 120
VBIAS dropout voltage(2) IOUT = 1.5A, VIN = VBIAS (Legacy Chip) 1.4 V
IOUT = 1.5A, VIN = VBIAS (New Chip) 1.43
ICL Current limit VOUT = 80% × VOUT(nom), (Legacy Chip) 1.8 4 A
VOUT = 80% × VOUT(nom), (New Chip) 2 5.5
IBIAS BIAS pin current IOUT = 0mA to 1.5A (Legacy Chip) 2 4 mA
IOUT = 0mA to 1.5A (New Chip) 1 2
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4V (Legacy Chip) 1 100 µA
VEN ≤ 0.4V, (New Chip) 0.85 2.75
IFB  Feedback pin current (3) IOUT = 50mA to 1.5A (Legacy Chip) –250 68 250 nA
IOUT = 50mA to 1.5A (New Chip) –30 0.15 30 nA
PSRR Power-supply rejection (VIN to VOUT) 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) 73 dB
1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) 60
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) 42
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) 30
Power-supply rejection (VBIAS to VOUT) 1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (Legacy Chip) 62
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (New Chip) 59
300kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 50
Vn Output noise voltage BW = 100Hz to 100kHz, IOUT = 1.5A, CSS = 1nF (Legacy Chip) 16 μVrms x Vout
BW = 100 Hz to 100 kHz, IOUT = 3A, CSS = 1nF (New Chip) 20
VTRAN %VOUT droop during load transient IOUT = 50mA to 1.5A at 1A/µs, COUT=none (Legacy Chip) 3.5 %VOUT
VTRAN %VOUT droop during load transient IOUT = 50mA to 1.5A at 1A/µs, COUT=2.2µF (New Chip) 1.7 %VOUT
tSTR Minimum start-up time RLOAD for IOUT = 1.5A, CSS = open (Legacy Chip) 100 µs
RLOAD for IOUT = 1.0A, CSS = open (New Chip) 250
ISS Soft-start charging current VSS = 0.4V, IOUT = 0mA (Legacy Chip) 0.500 0.730 1 µA
VSS = 0.4V, IOUT = 0mA (New Chip) 0.300 0.530 0.800
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis (Legacy Chip) 50 mV
(New Chip) 55
VEN(dg) Enable pin deglitch time 20 µs
IEN Enable pin current VEN = 5V (Legacy Chip) 0.1 1 µA
VEN = 5V (New Chip) 0.1 0.25
VIT PG trip threshold VOUT decreasing (Legacy Chip) 86.5 90 93.5 %VOUT
VOUT decreasing (New Chip) 85 90 94
VHYS PG trip hysteresis (Legacy Chip) 3 %VOUT
(New Chip) 2.5
VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT (Legacy Chip) 0.3 V
IPG = 1 mA (sinking), VOUT < VIT (New Chip) 0.12
IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT (Legacy Chip) 0.03 1 µA
VPG = 5.25 V, VOUT > VIT (New Chip) 0.001 0.05
TJ Operating junction temperature –40 125 ℃
TSD Thermal shutdown temperature Shutdown, temperature increasing (Legacy Chip) 155 ℃
Shutdown, temperature increasing (New Chip) 165
Reset, temperature decreasing 140
(1) Adjustable devices tested at 0.8V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal.
(3) IFB, ISNS current flow is out of the device.