SBVS355C June   2019  – May 2022 TPS745-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 TPS745-Q1 Comparison
      2. 7.3.2 Undervoltage Lockout (UVLO)
      3. 7.3.3 Shutdown
      4. 7.3.4 Foldback Current Limit
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Device Feedback Resistors
      2. 8.1.2 Input and Output Capacitor Selection
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Exiting Dropout
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Power-Good Function
      8. 8.1.8 Feed-Forward Capacitor (CFF)
      9. 8.1.9 Start-Up Sequencing
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Current
        2. 8.2.2.2 Thermal Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.6 Power Dissipation (PD)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD).

Equation 4. PD = (VIN – VOUT) × IOUT
Note:

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA).

Equation 5. TJ = TA + (RθJA × PD)

Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

Figure 8-5 and Figure 8-6 illustrate the functions of RθJA and ψJB versus copper (Cu) area and thickness. These plots are generated with a 101.6-mm x 101.6-mm x 1.6-mm printed circuit board (PCB) of two and four layers. For the four-layer board, the inner planes use a 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness. A 2 x 1 array of thermal vias of 300-µm drill diameter and 25-µm Cu plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane.

GUID-0EF9DB48-A7AD-4E9E-8D37-5D5878531E13-low.gifFigure 8-5 RθJA versus Cu Area for the WSON (DRV) Package
GUID-718061F0-34E2-4601-B585-037F6E466B81-low.gifFigure 8-6 ψJB versus Cu Area for the WSON (DRV) Package

As shown in Figure 8-7, each layer has a copper plane of equal area.

GUID-C7B6580A-313F-40C0-BE95-C37F74ACD955-low.gifFigure 8-7 Board parameters used for simulation

For a more comprehensive study of how thermal resistance varies with copper area and thickness, see the An empirical analysis of the impact of board layout on LDO thermal performance application report. As shown in Figure 8-8, modifying board layout to be more thermally enhanced can lower the RθJA value from 80.3°C/W to 46.8°C/W or better.

GUID-D64F0B76-7876-4897-B92A-1CF0C5B4A182-low.pngFigure 8-8 TPS745-Q1 (WSON) RθJA versus Board Layout