SLVSAI4E
September 2010 – September 2024
TPS74801-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics: IOUT = 50 mA
5.7
Typical Characteristics: IOUT = 1 A
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagrams
6.3
Feature Description
6.3.1
Programmable Soft-Start
6.3.2
Sequencing Requirements
6.3.3
Output Noise
6.3.4
Enable and Shutdown
6.3.5
Power Good
6.3.6
Internal Current Limit
6.3.7
Thermal Protection
6.4
Device Functional Modes
6.4.1
Normal Operation
6.4.2
Dropout Operation
6.4.3
Disabled
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Input, Output, and Bias Capacitor Requirements
7.2.2.2
Transient Response
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.1.1
Layout Recommendations and Power Dissipation
7.4.1.2
Estimating Junction Temperature
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Documentation Support
8.1.1
Related Documentation
8.1.2
Device Nomenclature
8.2
Receiving Notification of Documentation Updates
8.3
Support Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGW|20
MPQF122C
DRC|10
MPDS117L
Thermal pad, mechanical data (Package|Pins)
RGW|20
QFND012L
DRC|10
QFND709
Orderable Information
slvsai4e_oa
slvsai4e_pm
6.2
Functional Block Diagrams
Figure 6-1
Legacy Chip Functional Block Diagram
Figure 6-2
New Chip Functional Block Diagram