SLVSAI4E September   2010  – September 2024 TPS74801-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics: IOUT = 50 mA
    7. 5.7 Typical Characteristics: IOUT = 1 A
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Programmable Soft-Start
      2. 6.3.2 Sequencing Requirements
      3. 6.3.3 Output Noise
      4. 6.3.4 Enable and Shutdown
      5. 6.3.5 Power Good
      6. 6.3.6 Internal Current Limit
      7. 6.3.7 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input, Output, and Bias Capacitor Requirements
        2. 7.2.2.2 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Layout Recommendations and Power Dissipation
        2. 7.4.1.2 Estimating Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
      2. 8.1.2 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Typical Characteristics: IOUT = 50 mA

at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF (unless otherwise noted)

TPS74801-Q1 VIN Line Regulation
Legacy chip
Figure 5-1 VIN Line Regulation
TPS74801-Q1 VBIAS Line Regulation
Legacy chip
Figure 5-3 VBIAS Line Regulation
TPS74801-Q1 Load Regulation at Light Load
Legacy chip
Figure 5-5 Load Regulation at Light Load
TPS74801-Q1 Load Regulation
Legacy chip
Figure 5-7 Load Regulation
TPS74801-Q1 VIN Dropout Voltage vs IOUT and Temperature (TJ)
Legacy chip
Figure 5-9 VIN Dropout Voltage vs IOUT and Temperature (TJ)
TPS74801-Q1 VIN Dropout Voltage vs (VBIAS – VOUT) and Temperature (TA)
 
Figure 5-11 VIN Dropout Voltage vs (VBIAS – VOUT) and Temperature (TA)
TPS74801-Q1 VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
New chip
Figure 5-13 VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
TPS74801-Q1 VBIAS PSRR vs Frequency
New chip
Figure 5-15 VBIAS PSRR vs Frequency
TPS74801-Q1 VIN PSRR vs Frequency
New chip
Figure 5-17 VIN PSRR vs Frequency
TPS74801-Q1 VIN PSRR vs (VIN – VOUT)
New chip
Figure 5-19 VIN PSRR vs (VIN – VOUT)
TPS74801-Q1 Noise Spectral Density
New chip
Figure 5-21 Noise Spectral Density
TPS74801-Q1 BIAS Pin Current vs Output Current and Temperature (TJ)
New chip
Figure 5-23 BIAS Pin Current vs Output Current and Temperature (TJ)
TPS74801-Q1 BIAS Pin Current vs VBIAS and Temperature (TJ)
New chip
Figure 5-25 BIAS Pin Current vs VBIAS and Temperature (TJ)
TPS74801-Q1 Soft-Start Charging Current (ISS) vs Temperature (TJ)
New chip
Figure 5-27 Soft-Start Charging Current (ISS) vs Temperature (TJ)
TPS74801-Q1 Low-Level PG Voltage vs Current
New chip
Figure 5-29 Low-Level PG Voltage vs Current
TPS74801-Q1 Current Limit vs (VBIAS – VOUT)
New chip
Figure 5-31 Current Limit vs (VBIAS – VOUT)
TPS74801-Q1 VIN Line Regulation
New chip
Figure 5-2 VIN Line Regulation
TPS74801-Q1 VBIAS Line Regulation
New chip
Figure 5-4 VBIAS Line Regulation
TPS74801-Q1 Load Regulation at Light Load
New chip
Figure 5-6 Load Regulation at Light Load
TPS74801-Q1 Load Regulation
New chip
Figure 5-8 Load Regulation
TPS74801-Q1 VIN Dropout Voltage vs IOUT and Temperature (TJ)
New chip
Figure 5-10 VIN Dropout Voltage vs IOUT and Temperature (TJ)
TPS74801-Q1 VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
Legacy chip
Figure 5-12 VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
TPS74801-Q1 VBIAS PSRR vs Frequency
Legacy chip 
Figure 5-14 VBIAS PSRR vs Frequency
TPS74801-Q1 VIN PSRR vs Frequency
Legacy chip
Figure 5-16 VIN PSRR vs Frequency
TPS74801-Q1 VIN PSRR vs (VIN – VOUT)
Legacy chip
Figure 5-18 VIN PSRR vs (VIN – VOUT)
TPS74801-Q1 Noise Spectral Density
Legacy chip
Figure 5-20 Noise Spectral Density
TPS74801-Q1 BIAS Pin Current vs Output Current and Temperature (TJ)
Legacy chip
Figure 5-22 BIAS Pin Current vs Output Current and Temperature (TJ)
TPS74801-Q1 BIAS Pin Current vs VBIAS and Temperature (TJ)
Legacy chip
Figure 5-24 BIAS Pin Current vs VBIAS and Temperature (TJ)
TPS74801-Q1 Soft-Start Charging Current (ISS) vs Temperature (TJ)
Legacy chip
Figure 5-26 Soft-Start Charging Current (ISS) vs Temperature (TJ)
TPS74801-Q1 Low-Level PG Voltage vs Current
Legacy chip
Figure 5-28 Low-Level PG Voltage vs Current
TPS74801-Q1 Current Limit vs (VBIAS – VOUT)
Legacy chip
Figure 5-30 Current Limit vs (VBIAS – VOUT)