SLVSAI4E September 2010 – September 2024 TPS74801-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VREF | Internal reference (Adj.) | TA = 25°C | 0.796 | 0.8 | 0.804 | V | ||
VOUT | Output voltage range | VIN = 5 V, IOUT = 1.5 A | VREF | 3.6 | V | |||
Accuracy(1) | 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A (legacy chip) | –2 | ±0.5 | 2 | % | |||
2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A (new chip) | –1.35 | ±0.3 | 1.35 | |||||
ΔVOUT(ΔVIN) | Line regulation | VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (legacy chip) | 0.03 | %/V | ||||
VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (new chip) | 0.001 | |||||||
ΔVOUT(ΔIOUT) | Load regulation | 50 mA ≤ IOUT ≤ 1.5 A | 0.09 | %/A | ||||
VDO | VIN dropout voltage(2) | IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V (legacy chip) (3) | 60 | 165 | mV | |||
IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V (DRC: new chip) (3) | 50 | 100 | ||||||
IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V (RGW: new chip) (3) | 50 | 110 | ||||||
VBIAS dropout voltage(2) | IOUT = 1.5 A, VIN = VBIAS (legacy chip) | 1.31 | 1.6 | V | ||||
IOUT = 1.5 A, VIN = VBIAS (new chip) | 1.31 | 1.43 | ||||||
ICL | Output current limit | VOUT = 80% × VOUT(nom) | 2 | 5.5 | A | |||
IBIAS | BIAS pin current | (Legacy chip) | 1 | 2 | mA | |||
(New chip) | 1 | 1.2 | ||||||
ISHDN | Shutdown supply current (IGND) | VEN ≤ 0.4 V (legacy chip) | 1 | 50 | µA | |||
ISHDN (smart enable) | VEN ≤ 0.4 V (new chip) | 0.85 | 10 | |||||
IFB | Feedback pin current | (Legacy chip) | –1 | 0.15 | 1 | µA | ||
(New chip) | –30 | 0.15 | 30 | nA | ||||
PSRR | Power-supply rejection (VIN to VOUT) | 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (legacy chip) | 60 | dB | ||||
1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (new chip) | 69 | dB | ||||||
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (legacy chip) | 30 | |||||||
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (new chip) | 49 | |||||||
Power-supply rejection (VBIAS to VOUT) | 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (legacy chip) | 50 | ||||||
1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (new chip) | 59 | |||||||
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (legacy chip) | 30 | |||||||
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (new chip) | 50 | |||||||
Vn | Output noise voltage | BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF (legacy chip) | 25 × VOUT | μVrms | ||||
BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF (new chip) | 20 × VOUT | |||||||
tSTR | Minimum startup time | RLOAD for IOUT = 1.0 A, CSS = open (legacy chip) | 200 | µs | ||||
RLOAD for IOUT = 1.0 A, CSS = open (new chip) | 250 | |||||||
ISS | Soft-start charging current | VSS = 0.4 V (legacy chip) | 440 | nA | ||||
VSS = 0.4 V (new chip) | 530 | |||||||
VEN(hi) | Enable input high level | 1.1 | 5.5 | V | ||||
VEN(lo) | Enable input low level | 0 | 0.4 | V | ||||
VEN(hys) | Enable pin hysteresis | (Legacy chip) | 50 | mV | ||||
(New chip) | 55 | |||||||
VEN(dg) | Enable pin deglitch time | 20 | µs | |||||
IEN | Enable pin current | VEN = 5 V (legacy chip) | 0.1 | 1 | µA | |||
VEN = 5 V (new chip) | 0.1 | 0.3 | ||||||
VIT | PG trip threshold | VOUT decreasing | 85 | 90 | 94 | %VOUT | ||
VHYS | PG trip hysteresis | 3 | %VOUT | |||||
VPG(lo) | PG output low voltage | IPG = 1 mA (sinking), VOUT < VIT (legacy chip) | 0.3 | V | ||||
IPG = 1 mA (sinking), VOUT < VIT (new chip) | 0.125 | |||||||
IPG(lkg) | PG leakage current | VPG = 5.25 V, VOUT > VIT (legacy chip) | 0.1 | 1 | µA | |||
VPG = 5.25 V, VOUT > VIT (new chip) | 0.001 | 0.05 | ||||||
TSD | Thermal shutdown temperature | Shutdown, temperature increasing | 165 | ℃ | ||||
Reset, temperature decreasing | 140 | |||||||
RPULLDOWN | VBIAS = 5V, VEN = 0 V | 0.83 | kΩ |