SBVS074N
January 2007 – June 2024
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics: IOUT = 50 mA
5.7
Typical Characteristics: IOUT = 1 A
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagrams
6.3
Feature Description
6.3.1
Enable/Shutdown
6.3.2
Power Good
6.3.3
Internal Current Limit
6.3.4
Thermal Protection
6.4
Device Functional Modes
6.4.1
Normal Operation
6.4.2
Dropout Operation
6.4.3
Disabled
6.5
Programming
6.5.1
Programmable Soft-Start
6.5.2
Sequencing Requirements
7
Application and Implementation
7.1
Application Information
7.1.1
Adjusting the Output Voltage
7.1.2
Input, Output, and Bias Capacitor Requirements
7.1.3
Transient Response
7.1.4
Dropout Voltage
7.1.5
Output Noise
7.2
Typical Applications
7.2.1
FPGA I/O Supply at 1.5 V With a Bias Rail
7.2.1.1
Design Requirements
7.2.1.2
Detailed Design Procedure
7.2.1.3
Application Curves
7.2.2
FPGA I/O Supply at 1.5 V Without a Bias Rail
7.2.2.1
Design Requirements
7.2.2.2
Detailed Design Procedure
7.2.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.1.1
Estimating Junction Temperature
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
Device Nomenclature
8.1.2
Development Support
8.1.2.1
Evaluation Modules
8.1.2.2
Spice Models
8.2
Documentation Support
8.2.1
Related Documentation
8.3
Receiving Notification of Documentation Updates
8.4
Support Resources
8.5
Trademarks
8.6
Electrostatic Discharge Caution
8.7
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGW|20
MPQF122C
DRC|10
MPDS117L
Thermal pad, mechanical data (Package|Pins)
RGW|20
QFND012L
DRC|10
QFND013N
Orderable Information
sbvs074n_oa
sbvs074n_pm
6.5
Programming