SLVS237E August   1999  – March 2024 TPS766

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (Legacy Chip)
    5. 5.5 Thermal Information (New Chip)
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Characteristics: Supported ESR Range
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Power-Good Function
      6. 6.3.6 Output Pulldown
      7. 6.3.7 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Adjustable Device Feedback Resistors
        2. 7.2.2.2 Recommended Capacitor Types
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Input voltage range:
    • Legacy chip: 2.7V to 10V (13.5V absolute max)
    • New chip: 2.5V to 16V (18V absolute max)
  • Output voltage range:
    • Legacy chip: 1.5V to 5V (fixed) and 1.25V to 5.5V (adjustable)
    • New chip: 1.2V to 12V (fixed) and 0.8V to 14.6V (adjustable)
  • Output current: Up to 250mA
  • Output accuracy:
    • Legacy chip: 3% over load and temperature
    • New chip: 1% over load and temperature
  • Low quiescent current (IQ):
    • Legacy chip: 35μA (typ) with no load
    • New chip: 55μA (typ) with no load
  • IQ (disabled state):
    • Legacy chip: 10μA (max)
    • New chip: 4μA (max)
  • Dropout voltage (new chip):
    • Up to 225mV (typ) at 250mA (TPS76650)
  • High PSRR (new chip): 46dB at 1MHz
  • Internal soft-start time (new chip): 750µs (typical)
  • Overcurrent limiting and thermal protection
  • Stable with a 2.2µF or larger capacitor (new chip)
  • Open-drain power-good
  • Package: 8-pin, 4.9mm × 6mm SOIC (D)