The power-good circuit monitors the voltage at the output pin to indicate the health of the LDO output. When the output voltage falls below the PG threshold voltage (PG_TH), the PG pin open-drain output engages and pulls the PG pin close to GND. When the output voltage exceeds PG_TH + PG_Hysteresis, the PG pin becomes high impedance. The open-drain output requires a pullup resistor. By connecting a pullup resistor to an external supply, any downstream device receives power-good as a logic signal for use in sequencing. Additionally, tie the open-drain output to other open-drain outputs to implement an AND logic. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device.

When using a feed-forward capacitor (C_FF), the time constant for the LDO start-up is increased but the power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output. To avoid this issue, and to receive a valid PG output, make sure that the time constant of both the LDO start-up and the power-good output match. This matching is done by adding a capacitor in parallel with the power-good pullup resistor. For more information, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.

The state of PG is only valid when the device operates above the minimum input voltage of the device and power-good is asserted, regardless of the output voltage state when the input voltage falls below the UVLO threshold minus the UVLO hysteresis. When the input voltage falls below approximately 0.8V, there is not enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output pulled high. Connecting the power-good pullup resistor to the output voltage helps minimize this effect.