SLVS237E August   1999  – March 2024 TPS766

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (Legacy Chip)
    5. 5.5 Thermal Information (New Chip)
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Characteristics: Supported ESR Range
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Power-Good Function
      6. 6.3.6 Output Pulldown
      7. 6.3.7 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Adjustable Device Feedback Resistors
        2. 7.2.2.2 Recommended Capacitor Types
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

specified at TJ = –40°C to 125°C, VIN = VOUT(nom) + 1.0V or VIN = 2.5V (whichever is greater), IOUT = 10µA, EN = 0V, CIN = 1.0µF, COUT = 4.7µF (unless otherwise noted); typical values are at TJ = 25ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Output voltage (10 µA to 250 mA load) TPS76601 (for legacy chip) 1.25 V ≤ VOUT ≤ 5.5 V, TJ = +25°C VOUT V
1.25 V ≤ VOUT ≤ 5.5 V, TJ = –40 ℃ to 125°C 0.97 × VOUT 1.03 × VOUT
TPS76615 (for legacy chip) TJ = +25°C, 2.7 V < VIN < 10 V 1.5
TJ = –40°C to +125°C, 2.7 V < VIN < 10 V 1.455 1.545
TPS76618 (for legacy chip) TJ = +25°C, 2.8 V < VIN < 10 V 1.8
TJ = –40°C to +125°C, 2.7 V < VIN < 10 V 1.746 1.854
TPS76625 (for legacy chip) TJ = +25°C, 3.5 V < VIN < 10 V 2.5
TJ = –40°C to +125°C, 3.5 V < VIN < 10 V 2.425 2.575
TPS76627 (for legacy chip) TJ = +25°C, 3.7 V < VIN < 10 V 2.7
TJ = –40°C to +125°C, 3.7 V < VIN < 10 V 2.619 2.781
TPS76628 (for legacy chip) TJ = +25°C, 3.8 V < VIN < 10 V 2.8
TJ = –40°C to +125°C, 3.8 V < VIN < 10 V 2.716 2.884
TPS76630 (for legacy chip) TJ = +25°C, 4.0 V < VIN < 10 V 3.0
TJ = –40°C to +125°C, 4.0 V < VIN < 10 V 2.910 3.090
TPS76633 (for legacy chip) TJ = +25°C, 4.3 V < VIN < 10 V 3.3
TJ = –40°C to +125°C, 4.3 V < VIN < 10 V 3.201 3.399
TPS76650 (for legacy chip) TJ = +25°C, 6.0 V < VIN < 10 V 5.0
TJ = –40°C to +125°C, 6.0 V < VIN < 10 V 4.850 5.150
TPS766xx (for new chip), VOUT = 1.8 V TJ = –40 ℃ to 125 ℃, VOUT + 1 V ≤ VIN ≤ 16 V 0.9785 1.01 × VOUT
TPS766xx (for new chip), VOUT ≥ 3.3 V TJ = –40 ℃ to 125 ℃, VOUT + 1 V ≤ VIN ≤ 16 V 0.982 1.009 × VOUT
VFB Feedback voltage TPS76601 (for legacy chip) 1.25 V
TPS76601 (for new chip) 0.8
IQ Quiescent current (GND current), EN = 0 V For legacy chip 10 µA < IOUT < 250 mA, TJ = +25°C 35 µA
IOUT = 250 mA, TJ = –40 ℃ to 125 °C 50
For new chip IOUT = 0 mA (for adjustable only) 50 80
IOUT = 0 mA (for fixed only) 55 90
IOUT = 250 mA 1080
ΔVOUT(ΔVOUT) Output voltage line regulation (ΔVOUT/VOUT) For legacy chip VOUT(NOM) +1.0 V ≤ VIN ≤ 10 V, IOUT = 10 µA 0.01 %/V
For new chip VOUT(NOM) +1.0 V ≤ VIN ≤ 16 V, IOUT = 10 µA 0.005
ΔVOUT(ΔIOUT) Output voltage load regulation For legacy chip 10 µA ≤ IOUT ≤ 250 mA 0.5 %
For new chip 10 µA ≤ IOUT ≤ 250 mA 0.55 1.6
10 µA ≤ IOUT ≤ 250 mA 20 35 mV
Vn Output noise voltage For legacy chip BW = 300 Hz to 50 kHz, VOUT = 3.3 V , COUT = 4.7 µF 200 µVRMS
For new chip BW = 300 Hz to 50 kHz, VOUT = 3.3 V , IOUT = 100 mA,  COUT = 4.7 µF 165
BW = 10 Hz to 100 kHz, VOUT = 3.3 V, IOUT = 100 mA , COUT = 4.7 µF 195
TSD(shutdown) Thermal shutdown junction temperature For legacy chip 150 ºC
Thermal shutdown temperature For new chip Temperature increasing 173
TSD(reset) Thermal shutdown reset temperature Temperature falling 157
ICL Output current limit For legacy chip VOUT = 0 V 0.8 1.2 A
For new chip 0.725 0.8
ISTANDBY Standby current For legacy chip EN = VIN , 2.7 V < VIN < 10 V 1 µA
EN = VIN , 2.7 V < VIN < 10 V &  TJ = –40 ℃ to 125 ℃ 10
For new chip EN = VIN , 2.5 V < VIN < 16 V 0.9
EN = VIN , 2.5 V < VIN < 16 V &  TJ = –40 ℃ to 125 ℃ 6.75
IFB Feedback pin current For legacy chip VFB = 1.5 V 2 nA
For newchip 10 50 nA
EN High level enable input voltage For legacy chip 2 V
Low level enable input voltage 0.8
High level enable input voltage For new chip 2.5 V ≤ VIN ≤ 16 V 1.2
Low level enable input voltage 0.4
PSRR Power-supply ripple rejection For legacy chip VOUT = 3.3 V, IOUT = 10 µA, f = 1 kHz, TJ = 25 ℃ 63 dB
For new chip VOUT = 3.3 V, IOUT = 250 mA, f = 1 kHz, TJ = 25 ℃ 58
PG Minimum input voltage for valid PG For legacy chip IO(PG) = 300 µA 1.1
Trip threshold voltage (PGTH) VOUT decreasing 92 98 %VO
Hysteresis voltage (PGHysteresis) Measured at VOUT 0.5
Output low voltage VIN = 2.7 V, IOUT(PG) = 1 mA 0.15 0.4 V
Leakage current V(PG) = 5 V 1 µA
Minimum input voltage for valid PG For new chip IO(PG) = 300 µA 1.0
Trip threshold voltage (PGTH) VOUT decreasing 91 98.5 %VO
Hysteresis voltage (PGHysteresis) Measured at VOUT 0.45
Output low voltage VIN = 2.7 V, IOUT(PG) = 1 mA 0.12 0.3 V
Leakage current V(PG) = 5 V 2.1 µA
IEN Input current (EN) For legacy chip EN = 0V –1 0 1 µA
EN = VIN –1 0 1
For new chip EN = 0V –1 –0.5 1
EN = VIN –0.6 –0.025 0.4
VDO Dropout voltage TPS76628 (for legacy chip) IOUT = 250 mA 310 mV
IOUT = 250 mA, TJ = –40 ℃ to 125 ℃ 540
TPS76628 (for new chip) IOUT = 250 mA 310
IOUT = 250 mA, TJ = –40 ℃ to 125 ℃ 540
TPS76630 (for legacy chip) IOUT = 250 mA 270
IOUT = 250 mA, TJ = –40 ℃ to 125 ℃ 470
TPS76630 (for new chip) IOUT = 250 mA 270
IOUT = 250 mA, TJ = –40 ℃ to 125 ℃ 470
TPS76633 (for legacy chip) IOUT = 250 mA 230
IOUT = 250 mA, TJ = –40 ℃ to 125 ℃ 400
TPS76633 (for new chip) IOUT = 250 mA 260
IOUT = 250 mA, TJ = –40 ℃ to 125 ℃ 400
TPS76650 (for legacy chip) IOUT = 250 mA 140
IOUT = 250 mA, TJ = –40 ℃ to 125 ℃ 250
TPS76650 (for new chip) IOUT = 250 mA 250
IOUT = 250 mA, TJ = –40 ℃ to 125 ℃ 390
RPULLDOWN Output pull-down resistance TPS766xx (for new chip) EN = VIN = 16 V, VOUT = 2.5 V 1.8 KΩ
tSTR Start-up time TPS766xx (for new chip) TJ = 25 ℃ 750 µs