This device is designed to have a fast transient response and be stable with 10 μF capacitors. This combination provides high performance at a reasonable cost.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 230 mV at an output current of 1 A for the TPS76850-Q1) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 μA over the full range of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a shutdown mode; applying a TTL high signal to the enable (EN) input shuts down the regulator, reducing the quiescent current to less than 1 μA at TJ = 25°C.
Power good (PG) is an active-high output, which can be used to implement a power-on reset or a low-battery indicator.
The TPS768xx-Q1 is offered in 1.8-V, 2.5-V, 3.3-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS768xx-Q1 family is available in a 20-pin PWP package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS768xx-Q1 | HTSSOP (20) | 6.50 mm × 4.40 mm |
Changes from A Revision (September 2008) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 5 | I | Enable input |
FB/NC | 15 | I | Feedback input voltage for adjustable device (no connect for fixed options) |
GND | 3 | — | LDO ground |
GND/HSINK | 1, 2, 9, 10, 11, 12, 19, 20 | — | Ground and heatsink |
IN | 6, 7 | I | Input |
NC | 4, 8, 17, 18 | — | No connect |
OUT | 13, 14 | O | Regulated output voltage |
PG | 16 | O | Power-good output |
NC | 17 | — | No connect |
Thermal pad | — | — | Solder the thermal pad to the board. |
MIN | MAX | UNIT | |
---|---|---|---|
Input voltage, VI (2) | –0.3 | 13.5 | V |
Voltage at EN | –0.3 | VI + 0.3 | V |
Maximum PG voltage | 16.5 | V | |
Peak output current | Internally limited | ||
Output voltage, VO (OUT, FB) | 7 | V | |
Operating junction temperature, TJ | –40 | 150 | °C |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
Charged-device model (CDM), per AEC Q100-011 | All pins | ±500 | |||
Corner pins (1, 4, 5, and 8) | ±750 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VI | Input voltage(1) | 2.7 | 10 | V |
VO | Voltage at OUT | 1.2 | 5.5 | V |
IO | Output current(2) | 0 | 1 | A |
TA | Operating ambient temperature(2) | –40 | 125 | °C |
THERMAL METRIC(1) | TPS768xx-Q1 | UNIT | |
---|---|---|---|
PWP (HTSSOP) | |||
20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 39.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 25.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 22.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 21.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
Output voltage (10-μA to 1-A load)(1) |
TPS76801-Q1 | 5.5 V ≥ VO ≥ 1.5 V | TJ = 25°C | VO | V | |||
TJ = –40°C to 125°C | 0.98 × VO | 1.02 × VO | ||||||
TPS76818-Q1 | 2.8 V < VIN < 10 V | TJ = 25°C | 1.8 | |||||
TJ = –40°C to 125°C | 1.764 | 1.836 | ||||||
TPS76825-Q1 | 3.5 V < VIN < 10 V | TJ = 25°C | 2.5 | |||||
TJ = –40°C to 125°C | 2.45 | 2.55 | ||||||
TPS76833-Q1 | 4.3 V < VIN < 10 V | TJ = 25°C | 3.3 | |||||
TJ = –40°C to 125°C | 3.234 | 3.366 | ||||||
TPS76850-Q1 | 6 V < VIN < 10 V | TJ = 25°C | 5 | |||||
TJ = –40°C to 125°C | 4.9 | 5.1 | ||||||
Quiescent current (GND current), EN = 0 V(1) | TJ = 25°C 10 μA < IO < 1 A, TJ = 25°C | 85 | μA | |||||
TJ = –40°C to 125°C IO = 1 A, TJ = –40°C to 125°C | 125 | |||||||
Output voltage line regulation (ΔVO / VO) (1) (2) | TJ = 25°C VO + 1 V < VI ≤ 10 V, TJ = 25°C | 0.01 | %/V | |||||
Load regulation | 3 | mV | ||||||
Output noise voltage | TPS76818-Q1 | TJ = 25°C BW = 200 Hz to 100 kHz, CO = 10 μF, IC = 1 A, TJ = 25°C | 55 | μVrms | ||||
Output current limit | VO = 0 V | 1.7 | 2 | A | ||||
Thermal shutdown junction temperature | 150 | °C | ||||||
Standby current | EN = VI, 2.7 V < VI < 10 V |
TJ = 25°C | 1 | μA | ||||
TJ = –40°C to 125°C | 10 | |||||||
FB input current | TPS76801-Q1 | VFB = 1.5 V | 2 | nA | ||||
High-level enable input voltage | 1.7 | V | ||||||
Low-level enable input voltage | 0.9 | V | ||||||
Power-supply ripple rejection (1) | TJ = 25°C f = 1 kHz, CO = 10 μF, TJ = 25°C | 60 | dB | |||||
PG | Minimum input voltage for valid PG | IO(PG) = 300 μA | 1.1 | V | ||||
Trip threshold voltage | VO decreasing | 92 | 98 | %VO | ||||
Hysteresis voltage | Measured at VO | 0.5 | %VO | |||||
Output low voltage | VI = 2.7 V, IO(PG) = 1 mA | 0.15 | 0.4 | V | ||||
Leakage current | V(PG) = 5 V | 1 | μA | |||||
EN input current | EN = 0 V | –1 | 0 | 1 | μA | |||
EN = VI | –1 | 1 | ||||||
Dropout voltage (3) | TPS76833-Q1 | IO = 1 A | TJ = 25°C | 350 | mV | |||
TJ = –40°C to 125°C | 575 | |||||||
TPS76850-Q1 | TJ = 25°C | 230 | ||||||
TJ = –40°C to 125°C | 380 |