SLVS350J October   2002  – May 2019 TPS795

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      TPS79530 Ripple Rejection vs Frequency
      2.      TPS79530 vs Frequency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Shutdown
      2. 7.3.2 Start-Up
      3. 7.3.3 Undervoltage Lockout (UVLO)
      4. 7.3.4 Regulator Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Output Noise
        3. 8.2.2.3 Dropout Voltage
        4. 8.2.2.4 Programming the TPS79501 Adjustable LDO Regulator
      3. 8.2.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
      2. 10.1.2 Regulator Mounting
      3. 10.1.3 Thermal Considerations
      4. 10.1.4 Estimating Junction Temperature
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC(1)(2) TPS795(3) UNIT
DRB (VSON) DCQ (SOT-223)
6 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 46.8 74.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.1 44.5 °C/W
RθJB Junction-to-board thermal resistance 18.4 8.6 °C/W
ψJT Junction-to-top characterization parameter 0.7 3.2 °C/W
ψJB Junction-to-board characterization parameter 18.4 8.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.3 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB and DCQ packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
  1. i. DRB: The exposed pad is connected to the PCB ground layer through a 2-mm x 2-mm thermal via array.                         
    .ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3-mm x 2-mm thermal via array.                    
  2. i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
    .ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
  3. These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see Thermal Considerations and Estimating Junction Temperature of this data sheet.