SBVS097G march   2008  – june 2023 TPS799-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Dropout Voltage
      4. 7.3.4 Start-Up
      5. 7.3.5 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Feedback Capacitor Requirements (TPS79901-Q1 Only)
        3. 8.2.2.3 Output Noise
        4. 8.2.2.4 Transient Response
        5. 8.2.2.5 Minimum Load
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 8.4.1.2 Thermal Consideration
        3. 8.4.1.3 Power Dissipation
        4. 8.4.1.4 Package Mounting
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-55DE0892-25D8-47B4-8175-31B89F3B5B4C-low.gifFigure 5-1 DDC Package,5-Pin SOT-23(Top View)
GUID-4CBA78A8-7F4B-4EB9-8584-0898D30EA4FF-low.gifFigure 5-2 DRV Package,6-Pin WSON(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME SOT-23 WSON
EN 3 4 I Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used.
FB — 2 I Adjustable version only; this pin is the input to the control loop error amplifier, and is used to set the output voltage of the device.
GND 2 3, Pad — Ground. The pad must be tied to GND.
IN 1 6 I Input supply.
N/C — 5 — Not internally connected. This pin must either be left open or tied to GND.
NR 4 2 — Fixed-voltage versions only; connecting an external capacitor to this pin bypasses noise generated by the internal band gap. This capacitor allows output noise to be reduced to very low levels.
OUT 5 1 O Output of the regulator. A small capacitor (total typical capacitance ≥ 2 μF ceramic) is needed from this pin to ground to ensure stability.