SBVS254D February   2018  – August 2019 TPS7A05

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
      2.      Ground Current vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excellent Transient Response
      2. 7.3.2 Active Discharge
      3. 7.3.3 Low IQ in Dropout
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Enable
      6. 7.3.6 Internal Foldback Current Limit
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disable Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Special Considerations When Ramping Down VIN and Enable
      4. 8.1.4 Load Transient Response
      5. 8.1.5 Dropout Voltage
        1. 8.1.5.1 Behavior When Transitioning From Dropout Into Regulation
        2. 8.1.5.2 Behavior of Output Resulting From Line Transient When in Dropout
      6. 8.1.6 Undervoltage Lockout (UVLO) Operation
      7. 8.1.7 Power Dissipation (PD)
        1. 8.1.7.1 Estimating Junction Temperature
        2. 8.1.7.2 Recommended Area for Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Design Considerations
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Internal Foldback Current Limit

The internal foldback current-limit circuit is used to protect the LDO against high-load current faults or shorting events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power dissipation during short-circuit events while still allowing for the device to operate at its rated output current; see Figure 29.

A foldback example for this device is that when VOUT is 90% of VOUT(nom) the current limit is ICL(typical); however, if VOUT is forced to 0 V the current limit is ISC (typical).

In many LDOs the foldback current limit can prevent start-up into a constant-current load or a negatively-biased output. The foldback mechanism for this device goes into a brick-wall current limit when VOUT > 500 mV (typ), thus limiting current to ICL(typical) and, when VOUT is approximately 0 V, current is limited to ISC (typical) to ensure normal start-up into a variety of loads.

The foldback current limit is disengaged when IOUT < 1 mA (typical) to reduce IQ. As such, the current-limit loop takes longer to respond to a current-limit event when IOUT < 1 mA (typ).

Thermal shutdown can activate during a current-limit event because of the high power dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in current limit is not recommended.