SBVS400D december   2021  – august 2023 TPS7A14

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excellent Transient Response
      2. 7.3.2 Global Undervoltage Lockout (UVLO)
      3. 7.3.3 Enable Input
      4. 7.3.4 Internal Foldback Current Limit
      5. 7.3.5 Active Discharge
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disable Mode
  9. 8Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
      2. 8.1.2  Input, Output, and Bias Capacitor Requirements
      3. 8.1.3  Dropout Voltage
      4. 8.1.4  Behavior During Transition From Dropout Into Regulation
      5. 8.1.5  Device Enable Sequencing Requirement
      6. 8.1.6  Load Transient Response
      7. 8.1.7  Undervoltage Lockout Circuit Operation
      8. 8.1.8  Power Dissipation (PD)
      9. 8.1.9  Estimating Junction Temperature
      10. 8.1.10 Recommended Area for Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11.   Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

specified at TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.1 V, VBIAS = greater of 2.2 V or VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = 1.0 V, CIN = 1 μF, COUT = 2.2 μF, and CBIAS = 0.1 μF (unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT  Accuracy over temperature VOUT(NOM) + 0.1 V ≤ VIN ≤ 2.2 V,
Greater of 2.2 V or VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 1 A		 TJ = –40°C to +125°C, DRV package –1.25 1 %
TJ = –40°C to +125°C, YBK package –1.5 1
TJ = –40°C to +85°C –1 1
ΔVOUT / ΔVIN VIN line regulation  VOUT(NOM) + 0.1 V ≤ VIN ≤ 2.2 V, DRV package –3 3 mV
VOUT(NOM) + 0.1 V ≤ VIN ≤ 2.2 V, TJ = –40°C to +85°C, YBK package –2.5 2.5
ΔVOUT / ΔVBIAS VBIAS line regulation VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V, DRV package –3 ±0.15 3 mV
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V, TJ = –40°C to +85°C, YBK package –2.5 ±0.15 2.5
ΔVOUT / ΔIOUT Load regulation 1 mA ≤ IOUT ≤ 1 A 0.2 %/A
IQ(BIAS) Bias pin current IOUT = 0 mA, DRV package 43 µA
IOUT = 0 mA, TJ = –40°C to +85°C, YBK package 26
IOUT = 1 A, DRV package 17 mA
IOUT = 1 A, TJ = –40°C to +85°C, YBK package 12
IQ(IN) Input pin current(1) IOUT = 0 mA, DRV package 118 µA
IOUT = 0 mA, TJ = –40°C to +85°C 5.7
IGND Ground pin current IOUT = 1 A, DRV package 480 660 µA
IOUT = 1 A, TJ = –40°C to +85°C 480 620
ISHDN(BIAS) VBIAS  shutdown current VIN = 2.2 V, VBIAS = 5.5 V, VEN ≤ 0.2 V, DRV package 0.3 9 µA
VIN = 2.2 V, VBIAS = 5.5 V, VEN ≤ 0.2 V, TJ = –40°C to +85°C 0.3 3.8
ISHDN(IN) VIN  shutdown current VIN = 1.8 V, VBIAS = 5.5 V, VEN ≤ 0.2 V, DRV package 1 41 µA
VIN = 1.8 V, VBIAS = 5.5 V, VEN ≤ 0.2 V, TJ = –40°C to +85°C 1 9.2
ICL Output current limit VOUT = 0.95 × VOUT(NOM) 1.035 1.6 2.45 A
ISC Short circuit current limit VOUT = 0 V 600 mA
VDO(IN) VIN dropout voltage(2) VIN = 0.95 x VOUT(NOM),
IOUT = 1 A		 TJ = –40°C to + 125°C 99 mV
TJ = –40°C to + 85°C, DRV package 77
TJ = –40°C to + 85°C, YBK package 70
VDO(BIAS) VBIAS dropout voltage(2) VBIAS = greater of 1.7V or VOUT(nom) + 0.6 V,
VSENSE = 0.95 x VOUT(nom), IOUT = 1 A, DRV package		 1.115 V
VBIAS = greater of 1.7V or VOUT(nom) + 0.6 V,
VSENSE = 0.95 x VOUT(nom), IOUT = 1 A, YBK package		 1.1
VIN  PSRR VIN  power-supply rejection ratio f = 100 Hz IOUT = 3 mA 90 dB
IOUT = 500 mA 80
IOUT = 1 A 80
f = 1 kHz IOUT = 3 mA 90
IOUT = 500 mA 80
IOUT = 1 A 70
f = 10 kHz IOUT = 3 mA 70
IOUT = 500 mA 60
IOUT = 1 A 50
f = 100 kHz IOUT = 3 mA 60
IOUT = 500 mA 43
IOUT = 1 A 33
f = 1 MHz IOUT = 3 mA 60
IOUT = 500 mA 24
IOUT = 1 A 15
f = 1 MHz,
VIN = VOUT + 150 mV		 IOUT = 3 mA 69
IOUT = 500 mA 42
IOUT = 1 A 33
VBIAS PSRR VBIAS power-supply rejection ratio f = 1 kHz IOUT = 500 mA 65 dB
f = 100 kHz 45
f = 1 MHz 25
Vn Output voltage noise Bandwidth = 10 Hz to 100 kHz,
VOUT = 0.8 V, 5mA ≤ IOUT ≤ 1 A		 7.2 µVRMS
VUVLO(BIAS) Bias supply UVLO VBIAS rising 1.15 1.42 1.7 V
VBIAS falling 1.0 1.3 1.63
VUVLO_HYST(BIAS) Bias supply hysteresis VBIAS hysteresis 100 mV
VUVLO(IN) Input supply UVLO  VIN rising 584 603 623 mV
VIN falling 530 552 566
VUVLO_HYST(IN) Input supply hysteresis VIN hysteresis 50 mV
tSTR Start-up time(3)
 		 186 µs
VEN(HI) EN pin logic high voltage(4) 0.6 6 V
VEN(LOW) EN pin logic low voltage(4) 0 0.25 V
IEN EN pin current EN = 5.5 V, DRV package -25 10 25 nA
EN = 5.5 V,  TJ = –40°C to +85°C -20 10 20
RPULLDOWN Pulldown resistor VIN = 0.9 V, VOUT(nom) = 0.8 V, VBIAS = 1 V,
VEN = 0 V, P version only		 36 Ω
TSD Thermal shutdown temperature Shutdown, temperature rising 165 °C
Reset, temperature falling 140
(1) This is the current flowing from VIN to GND.
(2) Dropout is not measured for VOUT < 0.6 V. VBIAS dropout applies only for VBIAS of 2.2 V or greater.
(3) Startup time = time from EN assertion to 0.95 × VOUT(NOM).
(4) An input voltage within the minimum to maximum range is interpreted as the correct logic level.